3D Memory Cell Layout With Air Gaps for Low Parasitic Capacitance
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Solution Overview
Problem
The challenge in semiconductor memory devices is to increase memory cell density while reducing parasitic capacitance, which is hindered by structural limitations as memory cell size decreases.
Innovation Solution
A semiconductor device is designed with vertically stacked active layers, bit lines, capacitors, and a word line and back gate configuration, incorporating air gaps to reduce parasitic capacitance and enhance memory cell density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cell size is reduced to increase net die, then productivity is improved, but parasitic capacitance increases and manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The patent transitions from planar memory cell layout to three-dimensional vertical stacking. Multiple active layers are stacked vertically with bit lines extending in the horizontal direction, creating a 3D structure that increases storage density without proportionally increasing parasitic capacitance. This dimensional change allows more memory cells to be packed into the same footprint while maintaining electrical performance.
Solution Approach 2:
The memory device is divided into multiple discrete active layers stacked vertically, with each layer having its own bit line connections. This segmentation allows independent optimization of each layer and distributes the parasitic capacitance across multiple smaller units rather than concentrating it in a single large cell, thereby improving overall device performance while increasing density.
2Productivity
If memory cell size is reduced to increase net die, then productivity is improved, but manufacturing precision deteriorates
Solution Approach 1:
By moving to vertical stacking, the patent exploits the third dimension (height) for manufacturing. The vertical orientation allows standard fabrication processes to create well-defined layered structures with precise thickness control, avoiding the need to miniaturize lateral dimensions to the point where manufacturing precision becomes problematic.
Solution Approach 2:
Multiple active layers are nested vertically within the same device footprint, with each layer containing a complete memory cell structure. This nesting approach allows precise alignment and integration of multiple identical units using standard fabrication techniques, maintaining manufacturing precision while achieving high density through vertical accumulation rather than lateral compression.
3Productivity
If bit lines are placed close together to increase density, then productivity is improved, but parasitic capacitance between bit lines increases
Solution Approach 1:
Air gaps are introduced as intermediary spaces between adjacent bit lines. These air gaps act as electrical insulators with very low dielectric constant, effectively reducing the parasitic capacitance between closely spaced bit lines. The air gaps allow bit lines to be placed in close proximity for high density while maintaining low inter-line capacitance through the insulating air medium.
4Productivity
If word lines are placed close together to increase density, then productivity is improved, but interference between neighboring word lines increases
Solution Approach 1:
Vertical air gaps are positioned between adjacent word lines to serve as electrical insulators. These air gaps reduce capacitive coupling and prevent signal interference between neighboring word lines, allowing the device to achieve high density through close word line spacing without suffering from cross-talk or interference problems.
Data Source
AI summary
The present invention provides a highly integrated memory cell and a semiconductor device including the same. According to an embodiment of the present invention, the semiconductor device comprises: a plurality of active layers vertically stacked over a substrate; a plurality of bit lines connected to first ends of the active layers, respectively, and extended parallel to the substrate; line-shape air gaps disposed between the bit lines; a plurality of capacitors connected to second ends of the active layers, respectively; and a word line and a back gate facing each other with each of the active layers interposed therebetween, wherein the word line and the back gate are vertically oriented from the substrate.