3D Memory Device Air Gaps Reduce Capacitance
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Solution Overview
Problem
Current 3D memory devices face challenges in achieving higher storage capacity within a smaller form factor due to limitations in reducing capacitance and increasing breakdown voltage between metal lines, particularly in conventional process equipment compatibility.
Innovation Solution
The implementation of a 3D memory device structure featuring air gaps between conductive layers and a vertical conductive post, fabricated through a method involving alternating insulating layers, etching, and deposition processes to form voids and conductive layers, which reduces capacitance and increases breakdown voltage, allowing for thinner dummy insulating layers and increased cell density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional process equipment is used to fabricate 3D memory devices, then manufacturing compatibility is maintained, but storage density and cell size reduction are limited
Solution Approach 1:
The patent transitions from planar 2D memory architecture to three-dimensional stacked architecture with vertical channels extending through multiple conductive layers. This dimensional change enables significantly higher storage density by utilizing the vertical dimension for stacking multiple memory planes, while maintaining compatibility with conventional fabrication processes through adapted deposition and etching sequences.
Solution Approach 2:
The memory device is segmented into multiple stacked conductive layers separated by air gaps, with vertical memory structures passing through alternating layers. This segmentation allows independent formation and optimization of each layer stack, enabling higher overall density while managing process complexity through modular fabrication steps.
2Reliability
If air gaps are introduced between conductive layers to reduce capacitance, then electrical performance improves, but manufacturing process complexity increases
Solution Approach 1:
Air gaps are introduced as intermediary spaces between conductive layers to reduce parasitic capacitance and improve electrical performance. The air gaps are formed by selective removal of sacrificial insulating materials, creating natural dielectric regions that simplify the overall structure while enhancing electrical characteristics through reduced capacitive coupling between adjacent conductive layers.
Solution Approach 2:
Sacrificial insulating layers are temporarily deposited to define the positions of conductive layers and air gaps during fabrication, then selectively removed to create the final air gap structure. This approach allows precise control of air gap formation through standard deposition and etching processes, managing manufacturing complexity through temporary structural aids.
3Quantity of substance
If critical dimensions are reduced to increase storage capacity, then device density improves, but manufacturing precision requirements become more stringent
Solution Approach 1:
Multiple conductive layers and memory structures are nested vertically within a stacked architecture, with each layer containing smaller features that are integrated into the larger three-dimensional structure. This nesting approach allows continued scaling of critical dimensions within each layer while maintaining overall device functionality through the hierarchical organization of multiple stacked planes.
Data Source
AI summary
A three-dimensional memory device includes a substrate, a plurality of horizontal conductive layers, a plurality of vertical memory structures and a vertical conductive post. The conductive layers are located above the substrate, and immediately-adjacent two of the conductive layers are spaced by a first air gap. The memory structures pass through the conductive layers and are connected to the substrate. The conductive post is located between immediately-adjacent two of the memory structures and passes through the conductive layers and is connected to the substrate. The conductive post is spaced from immediately-adjacent edges of the conductive layers by a second air gap.