3D Memory Thermal Anneal Circuits for Endurance and Speed
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Solution Overview
Problem
Advanced memory technologies such as dielectric charge trapping memory, phase change memory, and ferroelectric memory in 3D structures suffer from limited endurance and operation speeds.
Innovation Solution
Implementing a thermal anneal process using a resistive component in thermal communication with memory cells, facilitated by a high-capacitance capacitor and a charge pump, to induce thermal anneal of memory cells, particularly in 3D stack configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If advanced memory technologies (dielectric charge trapping memory, phase change memory, ferroelectric memory) are implemented in 3D structures, then storage density is improved, but endurance and operation speed deteriorate
Solution Approach 1:
The patent applies preliminary action by implementing thermal anneal operations before and after programming/erasing cycles to prevent degradation of memory cells in 3D structures, thereby maintaining endurance while preserving the high storage density achieved through 3D configuration
2Quantity of substance
If advanced memory technologies (dielectric charge trapping memory, phase change memory, ferroelectric memory) are implemented in 3D structures, then storage density is improved, but operation speed deteriorates
Solution Approach 1:
The patent uses preliminary thermal anneal actions to prepare memory cells in optimal states before operations, and subsequent anneal actions to restore performance after operations, thereby maintaining high operation speeds while achieving high storage density through 3D structures
3Reliability
If thermal anneal operations are applied to heal degraded memory cells, then endurance is improved, but additional time and energy consumption are required
Solution Approach 1:
The patent implements periodic thermal anneal operations at specific intervals (before and after programming/erasing cycles) rather than continuous annealing, thereby improving endurance while minimizing time and energy consumption through scheduled maintenance cycles
4Reliability
If thermal anneal operations are applied to heal degraded memory cells, then reliability is improved, but energy consumption increases
Solution Approach 1:
The patent uses periodic thermal anneal operations at critical moments (before and after programming/erasing) rather than continuous operation, thereby improving reliability while minimizing energy consumption through intermittent maintenance cycles
Solution Approach 2:
The patent optimizes anneal operation parameters (temperature, duration, timing) to achieve effective healing of degraded memory cells while minimizing energy consumption, balancing reliability improvement with energy efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances the endurance and speed of memory operations by 'healing' degraded memory cells through a controlled thermal anneal process, improving the reliability and performance of 3D memory structures.
Implementation Method 1
a circuit to cause discharge of the capacitor via the resistive component to induce thermal anneal of the group of memory cells
Implementation Method 2
a capacitor; and a circuit to cause discharge of the capacitor via the resistive component to induce thermal anneal of the group of memory cells
Data Source
AI summary
An array of memory cells includes a resistive component disposed in thermal communication with a group of memory cells in the array of memory cells. A capacitor and a circuit to cause discharge of the capacitor via the resistive component induces thermal anneal of the group of memory cells. A charge pump and a circuit to enable the charge pump to precharge the capacitor can be used. The charge pump, the capacitor and the array of memory cells can be disposed on a single integrated circuit. The group of memory cells can be arranged in a 3D stack having multiple levels, and the resistive component can be “snaked” through the stack. The thermal anneal can be executing in timing coordination with erase operations in flash memory.