3D Memory Gate Stack With Anti-Ferroelectric Layer for Data Retention
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing the degree of integration and reliability, particularly in high-performance, high-speed, and multifunctional applications.
Innovation Solution
The semiconductor device incorporates a stacked structure with interlayer insulating layers and gate electrodes alternately stacked vertically, featuring a channel hole with a core region, channel layer, and anti-ferroelectric layers between the gate electrodes and dielectric layers, where the anti-ferroelectric material has a dynamic dielectric constant varying with the electric field, enhancing programming and erasing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional dielectric materials are used in memory devices, then device complexity is reduced, but programming efficiency and data retention are insufficient
Solution Approach 1:
The patent changes the dielectric parameter by using anti-ferroelectric material with high dielectric constant (k-value) instead of conventional dielectric materials. This parameter change enables superior charge retention capability and programming efficiency while maintaining device structure compatibility
Solution Approach 2:
The patent employs composite material structure by integrating anti-ferroelectric material with tunnel oxide layer and blocking oxide layer to form a multi-layer dielectric stack. This composite approach combines the high dielectric constant property of anti-ferroelectric material with the tunneling properties of thin oxide layers, achieving both high programming efficiency and excellent data retention
2Productivity
If degree of integration is increased, then productivity is improved, but reliability deteriorates
Solution Approach 1:
The patent transitions from planar two-dimensional memory structure to three-dimensional vertical structure by stacking multiple layers including anti-ferroelectric material, channel layers, and blocking layers vertically. This dimensional change enables significantly increased storage density while the anti-ferroelectric material ensures reliable charge retention in each vertical stack
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the programming efficiency, erasing efficiency, and data retention characteristics, while increasing the endurance and reliability of the semiconductor device, thereby addressing the integration and reliability challenges.
Implementation Method 1
the anti-ferroelectric material of the anti-ferroelectric layer interposed between the word lines and the channel layer has a dynamic dielectric constant varying in accordance with a magnitude of an electric field generated between the word lines and the channel layer
Data Source
AI summary
Semiconductor devices may include a stacked structure including interlayer insulating layers and gate electrodes alternately stacked in a vertical direction, a core region extending in the vertical direction in the stacked structure, a channel layer on a side surface of the core region and facing the gate electrodes and the interlayer insulating layers, a first dielectric layer, a data storage layer and a second dielectric layer, which are between the channel layer and the gate electrodes in order, and an anti-ferroelectric layer including a portion interposed between the first dielectric layer and a first gate electrode of the gate electrodes. The second dielectric layer may contact the channel layer. The anti-ferroelectric layer may be formed of an anti-ferroelectric material having a tetragonal phase.