3D Memory Stack Layout With Integrated Antifuse Repair Array
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Solution Overview
Problem
Existing 3D semiconductor memory devices face inefficiencies due to the large area occupied by antifuse devices in peripheral circuits, which are used for repairing defective memory cells.
Innovation Solution
A 3D semiconductor memory device design that stacks memory cells and antifuse cells vertically, with the antifuse cells integrated into a separate array region, allowing for a more efficient arrangement of peripheral circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If antifuse devices are used for repairing defective memory cells, then reliability is improved, but the area occupied by peripheral circuits increases
Solution Approach 1:
The patent transitions from a planar arrangement to a three-dimensional stacked architecture. Antifuse cells are integrated into vertical stacks alongside memory cells, utilizing the vertical dimension to accommodate repair functionality without expanding the lateral footprint of peripheral circuits. This dimensional transition enables compact integration while preserving defect repair capabilities.
Solution Approach 2:
The patent merges the antifuse array with the memory cell array by stacking them in the same vertical column. Both memory cells and antifuse cells share common structural elements such as substrates, insulating layers, and conductive patterns, consolidating what were previously separate peripheral and memory regions into an integrated three-dimensional structure.
2Productivity
If memory capacity is increased through high integration density, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent achieves high integration density by stacking multiple layers of memory cells and antifuse cells vertically. This three-dimensional arrangement multiplies the effective storage capacity within the same lateral area, dramatically increasing productivity without proportionally increasing the physical device footprint or manufacturing complexity.
Solution Approach 2:
The stacked structure serves multiple functions simultaneously: the lower stack provides memory storage, while the upper stack provides defect repair functionality. This multi-functional integration allows a single device structure to deliver both high-capacity storage and reliability enhancement, improving productivity without requiring separate dedicated regions for each function.
Data Source
AI summary
A semiconductor memory device includes a first stack structure including a memory cell region and an antifuse array region, the memory cell region including a plurality of memory cells and a plurality of cell capacitors, the plurality of memory cells being arranged three-dimensionally, and the antifuse array region including a plurality of antifuse cells that are arranged three-dimensionally; and a second stack structure on the first stack structure, the second stack structure including a core region and a peripheral circuit region, the core region at a location vertically overlapping the memory cell region, the core region being electrically connected to the memory cell region, and the peripheral circuit region at a location vertically overlapping the antifuse array region.