3D Semiconductor Memory Layout for Anti-Fuse Redundancy
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Solution Overview
Problem
Discarding semiconductor memory devices due to defects in only some unit cells is inefficient, as they can be restored by replacing failed cells with redundancy cells to improve yield.
Innovation Solution
A semiconductor memory device design incorporating vertical channel transistors and anti-fuse gate electrodes, allowing defective cells to be replaced with redundancy cells through a programming operation that destroys the anti-fuse gate insulating layer, thereby improving product yield and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If anti-fuse circuits are implemented in conventional planar configuration, then defect replacement functionality is achieved, but horizontal area is excessively occupied
Solution Approach 1:
The patent transitions from planar (2D) anti-fuse circuit layout to a vertical (3D) configuration where anti-fuse circuits are stacked above the substrate surface. This dimensional change allows the same functionality to be achieved while dramatically reducing the horizontal footprint of the device.
Solution Approach 2:
The anti-fuse circuits are nested within the vertical structure of the memory device, specifically positioned above the substrate and integrated with the vertical channel transistor architecture. This nesting approach allows multiple functional elements to occupy overlapping spatial regions, reducing overall device area.
2Productivity
If vertical channel transistors are used in cell array regions, then integration density is improved, but manufacturing complexity increases
Solution Approach 1:
The patent employs a unified vertical channel transistor design that serves multiple functions: it operates as the main storage transistor in cell array regions and as the anti-fuse transistor in peripheral circuit regions. This multi-functionality reduces the need for separate manufacturing processes for different transistor types, thereby reducing overall manufacturing complexity despite the advanced vertical architecture.
Solution Approach 2:
The patent utilizes controlled variations in geometric parameters (such as channel height, width, and doping profiles) of the vertical channel transistors to achieve different functional characteristics in different regions. By adjusting these parameters rather than changing the fundamental device architecture, the patent maintains manufacturing simplicity while achieving high integration density.
3Productivity
If redundancy cells are used to replace failed unit cells, then product yield is improved, but device area increases
Solution Approach 1:
The patent implements redundancy cells in a vertical stacking configuration rather than extending them horizontally. The anti-fuse circuits that control the redundancy cells are positioned vertically above the substrate, allowing the redundancy functionality to be integrated within the same horizontal footprint as the main cell array, thus avoiding area increase while maintaining improved product yield.
Data Source
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AI summary
A semiconductor memory device includes a first structure on a substrate and including core regions and a first peripheral circuit region, and a second structure on the first structure and including cell array regions and a second peripheral circuit region. The second structure includes a first active pattern in each of the cell array regions and perpendicular to an upper surface of the first structure, a word line adjacent to one side of the first active pattern and extending in a first direction parallel to the upper surface of the first structure, a bit line in contact with a lower surface of the first active pattern and extending in a second direction intersecting the first direction, a second active pattern in the second peripheral circuit region and perpendicular to the upper surface of the first structure, and an anti-fuse gate electrode on one side of the second active pattern.