3D Memory Array Built-In Self-Test via Concurrent Write Read
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Solution Overview
Problem
Conventional memory tests cannot be performed on 3D memory arrays due to the absence of a read port in the static array, which prevents direct reading of data, hindering the execution of tests like March tests that require sequential write and read cycles.
Innovation Solution
A method and apparatus using a memory built-in self-test (MBIST) controller that writes data to the static array, transfers it to the active array, and reads from the active array, allowing concurrent writing to the static array while reading from the active array, thereby modifying the March test to accommodate the absence of a read port in the static array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional March tests are performed on 3D memory arrays, then testing can be conducted, but the tests cannot be performed because the static array lacks a read port preventing direct data reading
Solution Approach 1:
The active array serves as an intermediary mediator between the static array and the test controller. Data is written to the static array, then transferred to the active array which has a read port, allowing the test controller to read the data. This intermediary approach enables testing of the static array without requiring it to have a read port.
Solution Approach 2:
The patent introduces a temporal dimension to the testing process by using overlapping write-read cycles. While data is being written to the static array in one cycle, data is being read from the active array in the same cycle, creating a pipeline effect that maintains test timing while accommodating the structural limitation.
2Ease of operation
If data transfer from static array to active array is added, then testing capability is enabled, but test timing is affected due to the additional transfer step
Solution Approach 1:
The patent implements continuous useful action by overlapping the write operation to the static array with the read operation from the active array. These operations occur concurrently in the same clock cycle, eliminating idle time and maintaining continuous testing activity without the additional transfer step causing timing delays.
Solution Approach 2:
Data is prepared and written to the static array in advance during one cycle, then immediately transferred to the active array and read in the same cycle. This preliminary action ensures that the test sequence can proceed without waiting for sequential completion of each operation.
3Productivity
If writes to static array and reads from active array are performed concurrently, then test timing is preserved, but coordination complexity increases
Solution Approach 1:
The test controller uses feedback signals to coordinate the concurrent write-read operations. Control signals are generated based on the test sequence requirements and the state of the memory arrays, enabling the controller to manage the overlapping operations and ensure correct data flow and timing.
Data Source
AI summary
A method and apparatus for testing a three dimensional (3D) memory including a static array and an active array. The method is performed by a memory built-in self-test (MBIST) controller, and includes writing data to the static array, transferring data from the static array to the active array, and reading data from the active array. The method further includes, in a plurality of subsequent cycles, writing data to the static array; transferring data from static array to the active array, and reading data from the active array, wherein said writing data for each subsequent cycle is performed concurrently with reading data for a previous cycle.