3D Volatile Memory Array Bonding for Smaller Control Logic Footprint
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Solution Overview
Problem
Microelectronic device designers face challenges in increasing integration density and performance while minimizing the footprint and complexity of control logic devices, which often consume more real estate than memory devices, limiting memory density and performance improvements.
Innovation Solution
The method involves forming microelectronic devices with independently constructed structures, including the formation of trenches and dielectric liners to create semiconductor pillars and word line structures, which are then filled with conductive materials to form gate electrodes, reducing the size and complexity of control logic devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If control logic devices are integrated with memory arrays to enable operations control, then memory device functionality is achieved, but control logic devices consume excessive real estate and increase device complexity
Solution Approach 1:
The patent divides the microelectronic device into separate assemblies: a first assembly containing the memory array and a second assembly containing the control logic devices. These assemblies are formed independently and then attached together, allowing each to be optimized separately and reducing overall device complexity while maintaining full functionality.
Solution Approach 2:
The patent transitions from a planar integration approach to a three-dimensional stacked architecture where memory and control logic are separated into different vertical layers/assemblies. This dimensional change allows independent optimization of each assembly and reduces the horizontal footprint while maintaining functional integration.
2Adaptability or versatility
If control logic devices are integrated with memory arrays, then operations control is enabled, but the horizontal footprint of the memory device increases
Solution Approach 1:
The patent moves control logic devices from the same horizontal plane as the memory array to a separate vertical assembly that is attached to the memory assembly. This vertical stacking approach maintains operations control capability while dramatically reducing the horizontal footprint of the overall device.
3Productivity
If processing conditions are optimized for memory array formation, then memory device performance is improved, but control logic device configurations and performance are limited
Solution Approach 1:
By separating the memory array and control logic devices into different assemblies formed at different times and under different processing conditions, the patent allows each assembly to be independently optimized. The memory assembly can be processed for maximum memory performance while the control logic assembly can be configured with flexible processing conditions suitable for its specific requirements.
4Quantity of substance
If feature dimensions are reduced to increase integration density, then memory density improves, but control logic device complexity increases
Solution Approach 1:
The patent separates control logic devices from the high-density memory array into a distinct assembly. This allows the memory array to achieve high integration density with reduced feature dimensions while the control logic assembly can use larger, less complex features that are easier to manufacture and less prone to defects.
Data Source
AI summary
Methods of forming a microelectronic device include forming a memory array structure including an array region having volatile memory cells within a horizontal area of the array region, the volatile memory cells respectively comprising a vertical channel access device and a storage node device vertically underlying and coupled to the vertical channel access device, forming a control circuitry structure comprising control logic devices, and bonding the control circuitry structure to a surface of the memory array structure vertically closer to the vertical channel access devices of the volatile memory cells than the storage node devices of the volatile memory cells.