3D Memory Array Cutting Structure for Lower Programming Interference
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Solution Overview
Problem
Planar memory cells face density limitations and increasing fabrication challenges as feature sizes approach a lower limit, leading to costly and inefficient memory devices.
Innovation Solution
A 3D memory architecture with interleaved conductive and dielectric layers, including word lines and drain select gate lines separated by dielectric layers, and cutting structures to divide memory arrays into independent blocks, reducing internal resistance and programming interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cell scaling is pursued, then memory density can be increased, but manufacturing complexity and cost increase significantly as feature sizes approach limits
Solution Approach 1:
The patent transitions from planar (2D) memory architecture to three-dimensional (3D) stacked memory architecture. Multiple memory arrays are stacked vertically in the first direction, with each array containing conductive layers and dielectric layers arranged in alternating sequences. This vertical stacking enables increased memory density without further planar scaling, thereby avoiding the manufacturing complexity associated with sub-10nm feature sizes while achieving higher storage capacity.
2Quantity of substance
If planar memory cell scaling is pursued, then memory density can be increased, but fabrication cost increases significantly
Solution Approach 1:
By stacking memory arrays vertically rather than scaling laterally, the patent achieves higher memory density through a different spatial dimension. This approach leverages existing 3D integration techniques and avoids the need for cutting-edge sub-10nm lithography, resulting in lower fabrication costs while achieving increased storage capacity.
3Quantity of substance
If 3D memory architecture is implemented, then memory density increases, but programming interference between adjacent memory blocks increases
Solution Approach 1:
The patent divides each memory array into multiple memory blocks separated by conductive layers. In the stack structure, conductive layers are positioned between memory blocks to electrically isolate them. This segmentation allows independent programming of each block, preventing programming interference between adjacent blocks while maintaining high memory density through vertical stacking.
Solution Approach 2:
Conductive layers serve as intermediary structures between memory blocks. These conductive layers act as physical and electrical barriers that isolate adjacent memory blocks, preventing programming interference while allowing the overall 3D stacked structure to maintain high density. The conductive layers mediate the interaction between memory blocks, enabling independent operation of each block.
4Quantity of substance
If 3D memory architecture is implemented, then memory density increases, but control precision over individual memory blocks decreases
Solution Approach 1:
By segmenting each memory array into distinct memory blocks separated by conductive layers, the patent enables independent and precise control of each block. The conductive layers provide clear electrical boundaries that allow selective addressing and programming of individual blocks, maintaining high control precision even as memory density increases through vertical stacking.
Data Source
AI summary
A three-dimensional memory device includes memory arrays stacking in a first direction. Each of the memory arrays includes a stack structure including interleaved conductive layers and first dielectric layers extending in a second direction perpendicular to the first direction and a third direction perpendicular to the first direction and the second direction. The conductive layers include word lines and a drain select gate line, and the drain select gate line is separated by a second dielectric layer in the second direction.