3D Memory Array Layout for Accurate In-Memory Computing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In-memory-computing methods in three-dimensional memory devices suffer from inaccuracies due to voltage drops on wires, which are exacerbated by larger memory arrays, leading to increased computing errors.
Innovation Solution
A three-dimensional memory device with a 3D memory array, encoding circuit, and sensing circuit, where input voltages and output currents are received and transmitted through non-parallel array sides, utilizing multiple sub-circuits to facilitate in-memory-computing and reduce the impact of voltage drops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If in-memory computing is performed using traditional methods, then computing can be directly performed in memory to enhance speed and efficiency, but voltage drop on wires causes inaccurate computing results
Solution Approach 1:
The patent divides the memory array into multiple sub-arrays (first sub-array, second sub-array, etc.) with separate encoding circuits and sensing circuits for each. This segmentation allows independent computation and sensing in each sub-array, reducing the impact of voltage drops on wire accuracy by localizing the computation to smaller regions with shorter wire paths.
Solution Approach 2:
The patent introduces auxiliary current paths through additional encoding circuits and sensing circuits that act as intermediaries. These auxiliary circuits provide alternative current paths that can compensate for voltage drops in the main computation path, enabling more accurate sensing of computation results despite wire resistance.
2Quantity of substance
If larger memory array is used to increase computing capacity, then more memory cells are available for computation, but computing errors increase due to larger voltage drops on wires
Solution Approach 1:
The patent segments the large memory array into multiple smaller sub-arrays, each with its own encoding and sensing circuits. This allows the system to maintain large total capacity while keeping individual computation units small enough to minimize voltage drop effects, thereby maintaining accuracy across large-scale computations.
Solution Approach 2:
The patent adds a dimensional approach by introducing multiple parallel current paths through different encoding and sensing circuits. Instead of relying on a single current path through the entire large array, the system uses multiple dimensions of current flow to parallelize computation, reducing the effective wire length and voltage drop impact.
3Measurement precision
If multiple matrices are used to eliminate voltage drop error, then computing accuracy improves, but the amount of computing increases greatly
Solution Approach 1:
The patent segments the computation into parallel sub-computations across multiple sub-arrays that operate simultaneously. Each sub-array performs a portion of the computation independently, and the results are combined by the processing circuit. This segmentation reduces the total computing burden compared to using multiple matrices sequentially, while maintaining accuracy through localized computation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves the accuracy of in-memory-computing by utilizing multiple current paths and reducing the effect of voltage drops on wires, enhancing the computing process.
Implementation Method 1
The in-memory computing is performed by inputting voltages to the memory array and sensing outputted currents from the memory array
Data Source
AI summary
A three-dimensional (3D) memory device comprising a 3D memory array, an encoding circuit, a sensing circuit and a processing circuit is provided in present disclosure. The 3D memory array comprises multiple two-dimensional (2D) memory arrays and is configured to receive multiple input voltages and output multiple output currents. Each 2D memory array comprises multiple memory cells and a four-array-side edge. The encoding circuit and the sensing circuit are coupled to the processing circuit and the four-array-side edge, and respectively configured to input the input voltages and receive the output currents. The processing circuit is configured to perform an in-memory-computing according to the input voltages and the output currents. The four-array-side edge has multiple array sides. When one of the array sides is configured to receive the input voltages, another is configured to output the output currents, wherein the one of the array sides is not parallel to the another.