3D Memory Array With Alternating Conductive Pillars
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Solution Overview
Problem
Conventional 3D cross point memory arrays face challenges in reducing memory cell size due to high fabrication costs and variability in layer characteristics, leading to reliability and performance issues, as each layer requires separate patterning steps and differs in thermal budget.
Innovation Solution
A 3D memory array design featuring alternately arranged word line layers, conductive pillar arrays, and bit line layers, where conductive pillars are fabricated in the same or two patterning steps, ensuring identical characteristics and thermal budgets across layers, reducing memory cell size to 2F2 and enhancing density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If separate patterning steps are used for each memory layer, then memory cell size can be reduced, but fabrication cost increases and layer characteristics become variable
Solution Approach 1:
The patent merges the patterning process for multiple memory layers into a single unified patterning step. Conductive pillars for both first and second memory elements are formed simultaneously using one photolithography and etching sequence, eliminating the need for separate patterning steps for each layer. This reduces fabrication cost while maintaining reduced memory cell size of 2F2.
Solution Approach 2:
The patent segments the memory array into alternating first and second memory elements that share common word lines and bit lines. This segmentation allows both memory types to be formed in the same patterning step while maintaining distinct structural characteristics for optimal performance.
2Area of moving object
If separate patterning steps are used for each memory layer, then memory cell size can be reduced, but device variability increases
Solution Approach 1:
By combining the patterning of first and second conductive pillars into a single process step, the patent ensures that both memory layers experience identical manufacturing conditions including photoresist coating, exposure, development, and etching parameters. This eliminates variability in layer characteristics such as pillar width, height, and material composition that would arise from separate patterning steps.
Solution Approach 2:
The patent creates homogeneous manufacturing conditions for all memory elements by using a unified patterning approach. All conductive pillars regardless of whether they form first or second memory elements are processed simultaneously under identical conditions, ensuring uniform electrical characteristics and reducing device-to-device variability.
3Productivity
If lower memory layer is processed first, then upper layers can be formed, but lower layer reliability decreases due to higher thermal budget
Solution Approach 1:
The patent inverts the conventional sequential layer formation approach by forming both first and second memory elements simultaneously in the same patterning step. This eliminates the thermal budget accumulation problem where lower layers would be repeatedly exposed to high temperatures during subsequent processing of upper layers, thereby preserving lower layer reliability while maintaining productive multi-layer fabrication.
Data Source
AI summary
A 3-D memory is provided. Each word line layer has word lines and gaps alternately arranged along a first direction. Gaps include first group and second group of gaps alternately arranged. A first bit line layer is on word line layers and has first bit lines along a second direction. A first conductive pillar array through word line layers connects the first bit line layer and includes first conductive pillars in first group of gaps. A first memory element is between a first conductive pillar and an adjacent word line. A second bit line layer is below word line layers and has second bit lines along the second direction. A second conductive pillar array through word line layers connects the second bit line layer and includes second conductive pillars in second group of gaps. A second memory element is between a second conductive pillar and an adjacent word line.