3D Memory Array Using Intersecting Electrode Pillars and Conductive Layers
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Solution Overview
Problem
The high manufacturing costs associated with three-dimensional (3D) memory devices due to the numerous critical lithography steps required for each memory layer, which limits the scalability and cost-effectiveness of these devices despite their potential for higher storage density.
Innovation Solution
A 3D memory device architecture featuring an array of electrode pillars intersected by conductive layers with memory elements at the interface regions, utilizing two-dimensional decoding for electrode pillars and three-dimensional decoding for conductive layers, which reduces the need for critical lithography steps and allows for a higher number of memory planes without increasing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple layers of memory cells are stacked to achieve greater storage capacity, then storage density is improved, but the number of critical lithography steps increases, leading to higher manufacturing costs
Solution Approach 1:
Multiple memory layers share common word lines and bit lines, merging the interconnect structures across layers. This reduces the total number of lithography steps required compared to manufacturing separate layers, as the common lines are formed once and serve multiple layers simultaneously
Solution Approach 2:
The patent transitions from planar 2D memory architecture to 3D stacked architecture by adding the vertical dimension. Multiple memory layers are stacked vertically with shared interconnects, enabling higher storage capacity without proportionally increasing lithography complexity
2Ease of manufacture
If critical lithography steps are minimized to reduce manufacturing costs, then ease of manufacture is improved, but the ability to create reliable small memory elements may be compromised
Solution Approach 1:
The memory structure is segmented into distinct functional regions: access devices formed with standard lithography, and memory elements formed in interface regions between electrode pillars and conductive layers. This segmentation allows different manufacturing precision requirements for different functional areas
Solution Approach 2:
The patent introduces intermediate structures (electrode pillars and conductive layers) that mediate between the access devices and the memory elements. These intermediates are formed using standard lithography processes, while the actual memory elements are created in the interface regions through material deposition and processing, decoupling the lithography precision requirements from the final memory element dimensions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables a low-cost, high-density memory solution by minimizing lithography steps and allowing for a larger number of memory planes, thereby enhancing storage capacity while maintaining affordability.
Implementation Method 1
The electrode pillars comprise a doped polysilicon having a first conductivity type, and the plurality of conductive layers comprise a doped polysilicon having an opposite conductivity type, thereby forming a diode including a p-n junction in the interface regions
Implementation Method 2
A layer of anti-fuse material, such as a silicon oxide, or other programmable resistance material, is formed between the anode and the cathode of the diode
Data Source
AI summary
A 3D memory device is based on an array of electrode pillars and a plurality of electrode planes that intersect the electrode pillars at interface regions that include memory elements that comprise a programmable element and a rectifier. The electrode pillars can be selected using two-dimensional decoding, and the plurality of electrode planes can be selected using decoding on a third dimension.