3D Memory Cell Array Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
The challenge of reducing parasitic capacitance and increasing capacitance in memory cells is hindered by structural limitations in conventional two-dimensional semiconductor devices, limiting the integration density of memory devices.
Innovation Solution
A semiconductor device with a three-dimensional structure featuring vertically stacked memory cell arrays separated by a slit, allowing for independent plate voltage application and reduced parasitic capacitance, while maintaining high integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cell size is reduced to increase net die, then integration density improves, but parasitic capacitance increases and capacitance decreases
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell structures to three-dimensional vertically stacked structures. Multiple capacitor layers are stacked in the vertical direction (first direction) to increase capacitance without increasing planar area, while the second direction spacing and slit structure control parasitic capacitance between adjacent stacked capacitors
Solution Approach 2:
The memory cell array is divided into multiple independently controllable capacitor stacks along the second direction. Each stack can have independent plate voltage applied through separated common plates, allowing selective operation and reducing coupled parasitic capacitance effects across the entire array
2Area of stationary object
If memory cell size is reduced, then net die increases, but capacitance decreases
Solution Approach 1:
The invention utilizes the vertical dimension (first direction) to stack multiple capacitors, thereby increasing total capacitance without increasing the planar footprint (net die). The capacitance is accumulated through vertical stacking while maintaining compact lateral dimensions
3Productivity
If three-dimensional stacked structure is implemented, then integration density improves, but parasitic capacitance between adjacent capacitors increases
Solution Approach 1:
A slit structure is introduced between adjacent capacitor stacks in the second direction to electrically isolate and physically separate them. This extraction of the separating element reduces parasitic capacitance coupling between neighboring stacked capacitors while preserving the vertical stacking benefit for integration density
Solution Approach 2:
The spacing between common plates is optimized locally in the second direction to balance capacitance retention and parasitic reduction. The slit positioning and dimensions are specifically designed to minimize parasitic capacitance at critical interfaces while maintaining overall capacitor performance
Data Source
AI summary
A semiconductor device includes: a first common plate extending vertically in a first direction; a second common plate which is spaced apart from the first common plate in a second direction and extends vertically in the first direction; a slit formed between the first common plate and the second common plate; a first memory cell array sharing the first common plate and including first capacitors that are vertically stacked in the first direction; and a second memory cell array sharing the second common plate and including second capacitors that are vertically stacked in the first direction.