3D Memory Array Vertical Stacking Reduces Contact Area

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Solution Overview

Problem

Existing three-dimensional memory arrays face challenges in reducing contact area between storage elements and conductive lines, leading to increased programming current and reduced sensing accuracy, while also limiting memory cell density.

Innovation Solution

The proposed three-dimensional memory array design features conductive lines separated by insulation material with conductive extensions and storage elements having two distinct contacts at different ends of each line, reducing the contact area and enhancing voltage threshold windows, thereby improving performance and density.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the contact area between storage elements and conductive lines is reduced, then programming current decreases and sensing accuracy improves, but memory cell density is limited

Engineering Contradiction:
Improvesensing accuracyVSAvoidmemory cell density
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent transitions from two-dimensional planar contacts to three-dimensional vertical stacking, where storage elements are positioned above and below conductive lines at different heights. This dimensional change allows multiple storage elements to share common conductive lines without increasing contact area, thereby improving density while maintaining sensing accuracy.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements a nested structure where storage elements are concentrically arranged around conductive extensions, with inner and outer storage elements sharing the same conductive line. This nesting approach maximizes the use of available space and enables higher density without proportionally increasing the contact area.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Loss of energy

If the contact area between storage elements and conductive lines is reduced, then programming current decreases, but memory cell density is limited

Engineering Contradiction:
Improveprogramming currentVSAvoidmemory cell density
Core Design Contradiction:
Loss of energyVSProductivity

Solution Approach 1:

By stacking storage elements vertically at different heights above and below conductive lines, the patent enables multiple cells to share common conductive lines. This reduces the total contact area and programming current while increasing memory cell density through the third dimension.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

Conductive lines serve multiple functions by acting as both word lines for selecting rows of memory cells and as shared contact paths for multiple storage elements at different levels. This multi-functionality reduces the overall number of conductive lines needed, decreasing contact area and programming current while maintaining high density.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Productivity

If storage elements are positioned at multiple heights above and below conductive lines, then memory cell density increases, but fabrication complexity increases

Engineering Contradiction:
Improvememory cell densityVSAvoidfabrication complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent divides the memory structure into discrete vertical stacks, each containing storage elements at specific heights. This segmentation allows for modular fabrication where each stack can be formed independently through sequential deposition and etching steps, making the complex three-dimensional structure manufacturable using standard semiconductor processing techniques.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design reduces the programming current and enhances sensing accuracy, achieving up to double the memory cell density compared to previous arrays, with a smaller contact area that can be three to four times less than previous designs, improving overall performance.

Implementation Method 1

resistive memory cells that can store data based on the resistance state of a storage element (e.g., a resistive memory element having a variable resistance)

Methodology Applied
Scientific EffectVariable resistance: Electrical Resistance

Implementation Method 2

a plurality of conductive lines separated from one other by an insulation material

Methodology Applied
Scientific EffectElectrical insulation: Dielectric

Data Source

PatentEP3607595B1Three dimensional memory array and fabrication method thereof
Publication Date: 2024.01.03 MICRON TECHNOLOGY INC
  • EP3607595B1 patent drawingFigure 1A
  • EP3607595B1 patent drawingFigure 1B
  • EP3607595B1 patent drawingFigure 2A

AI summary

The present disclosure includes three dimensional memory arrays, and methods of processing the same. A number of embodiments include a plurality of conductive lines separated from one other by an insulation material, a plurality of conductive extensions arranged to extend substantially perpendicular to the plurality of conductive lines, and a storage element material formed around each respective one of the plurality of conductive extensions and having two different contacts with each respective one of the plurality of conductive lines, wherein the two different contacts with each respective one of the plurality of conductive lines are at two different ends of that respective conductive line.