3D Memory Array Contact Vias Within Memory-Opening-Free Regions
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in efficiently forming layer contact via structures within memory array regions, which affects the density and performance of memory arrays.
Innovation Solution
A method involving the formation of an alternating stack of insulating and sacrificial material layers, followed by the creation of memory openings and fill structures, and the replacement of sacrificial materials with electrically conductive layers and via fill structures, including insulating spacers to form layer contact assemblies that contact the conductive layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If layer contact via structures are formed in memory array regions, then active memory area increases and chip size reduces, but manufacturing complexity increases
Solution Approach 1:
The memory array is divided into memory openings and memory-opening-free areas, with layer contact via structures selectively formed in the latter. This segmentation allows simultaneous formation of memory structures and contact via structures through the same alternating stack, increasing active memory area while managing manufacturing complexity through systematic process division.
Solution Approach 2:
The patent utilizes vertical stacking to create three-dimensional memory structures with alternating insulating and electrically conductive layers. By forming layer contact via structures that contact specific conductive layers at different heights, the invention effectively uses the vertical dimension to increase functional density without proportionally increasing chip footprint, thereby improving area efficiency.
2Length of stationary object
If layer contact via structures are integrated in memory array regions, then chip size reduces, but process complexity increases
Solution Approach 1:
The patent merges the formation of memory structures and layer contact via structures into a unified process flow. Both structures are formed within the same alternating stack of insulating and electrically conductive layers using integrated lithography, etching, and filling processes. This merging reduces overall process complexity compared to separate formation approaches while achieving compact chip size.
Solution Approach 2:
The alternating stack of insulating and electrically conductive layers is formed preliminarily before defining the final memory opening patterns. This preliminary formation of the layered structure enables subsequent selective formation of both memory structures and layer contact via structures through the same stack, reducing overall process complexity while achieving reduced chip size.
3Area of stationary object
If memory openings are arranged to provide memory-opening-free areas, then active memory area increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies different structural configurations to different regions: memory openings are formed in regions requiring high-density storage, while memory-opening-free areas are created in regions optimized for layer contact via structure formation. This local differentiation allows each region to be optimized for its specific function with appropriate manufacturing precision requirements, overall increasing active memory area.
Data Source
AI summary
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, an array of memory openings vertically extending through the alternating stack, memory-opening-free areas located in the array of the memory openings in a plan view, an array of memory opening fill structures located in the array of memory openings, and layer contact assemblies located within the memory-opening-free areas in the plan view. Each of the memory opening fill structures includes a respective vertical semiconductor channel and respective memory elements located at levels of the electrically conductive layers. Each of the layer contact assemblies includes a respective layer contact via structure contacting a respective one of the electrically conductive layers, and a respective insulating spacer that laterally surrounds the respective layer contact via structure.