3D Memory Cell Array Layout With Segmented Multi-Directional Wiring
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge of further enhancing the three-dimensionality of semiconductor memory devices to improve integration and performance is ongoing.
Innovation Solution
A semiconductor memory device design featuring a memory cell array with sub-array columns and layers arranged in multiple directions, incorporating specific wiring and gate structures, and a transistor layer with sense amplifier units to enhance connectivity and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the degree of integration is increased to improve memory capacity, then the device complexity and manufacturing difficulty increase
Solution Approach 1:
The memory cell array is divided into multiple sub-array columns arranged in a first direction, with each sub-array column containing multiple sub-arrays. This segmentation allows the large memory structure to be managed as smaller, more manageable units, reducing overall device complexity while maintaining high integration capacity.
Solution Approach 2:
The patent implements a three-dimensional architecture with sub-arrays arranged in a second direction (intersecting the first direction) and memory portions arranged in a third direction (intersecting both first and second directions). This multi-dimensional arrangement increases memory capacity without proportionally increasing planar device complexity.
2Adaptability or versatility
If more wiring layers and gate electrodes are added to improve connectivity, then the manufacturing precision requirements increase
Solution Approach 1:
The wiring system is segmented into first wirings extending in the third direction, second wirings arranged in the third direction, and fourth wirings extending in the second direction. This segmentation of wiring functions allows each wiring type to be manufactured and controlled independently, reducing overall manufacturing precision requirements.
Solution Approach 2:
The patent utilizes three-dimensional wiring arrangements with conductive layers extending in multiple directions (first, second, and third directions). This vertical stacking and multi-directional routing provides alternative pathways for connectivity, reducing the precision demands on any single wiring layer while achieving comprehensive adaptability.
3Quantity of substance
If sub-array columns are arranged in multiple directions to improve integration density, then the device structure becomes more complex
Solution Approach 1:
The patent arranges sub-array columns in a first direction, sub-arrays within each column in a second direction (intersecting the first), and memory portions within each sub-array in a third direction (intersecting both first and second directions). This systematic three-dimensional arrangement maximizes integration density while maintaining a structured, manageable complexity through clear spatial organization.
Data Source
AI summary
A semiconductor memory device comprises a memory cell array. The memory cell array comprises sub arrays. The sub array comprises: memory portions; first semiconductor layers electrically connected to memory portions; first gate electrodes respectively facing first semiconductor layers; a first wiring electrically connected to first semiconductor layers; second wirings connected to first gate electrodes; second semiconductor layers electrically connected to first end portions of second wirings; second gate electrodes facing second semiconductor layers; and a third wiring electrically connected to second semiconductor layers. The memory cell array comprises fourth wirings that extend in one direction across the sub arrays and are connected to second gate electrodes.