3D Memory Opening Arrays With Asymmetric Pitch and Bit Line Layout
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in efficiently arranging memory openings and forming effective memory structures that optimize pitch and offset configurations, leading to suboptimal performance and manufacturing complexity.
Innovation Solution
A three-dimensional memory device is designed with an alternating stack of insulating and conductive layers, featuring periodic two-dimensional arrays of memory openings with specific pitch and offset arrangements, and memory opening fill structures that include vertical semiconductor channels and drain regions, connected by bit lines extending along a particular horizontal direction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If memory openings are arranged in conventional configurations, then manufacturing processes are simpler, but device density and performance are suboptimal
Solution Approach 1:
The patent implements an asymmetric pitch arrangement where the first pitch between adjacent memory openings in a column is different from the second pitch between adjacent memory openings in neighboring columns. Specifically, the first pitch ranges from 0.5-2.0 times the memory opening diameter while the second pitch ranges from 0.3-0.8 times the diameter. This asymmetric configuration optimizes electrical isolation and signal integrity while maintaining manufacturability through standard lithographic processes.
Solution Approach 2:
The patent transitions from conventional two-dimensional memory opening arrangements to a three-dimensional stacked configuration with alternating conductive and insulating layers. Multiple memory openings are vertically stacked above each other, creating a columnar structure that extends through the substrate. This vertical dimension multiplication significantly increases device density without proportionally increasing the lateral footprint, thereby improving area efficiency while maintaining manageable manufacturing complexity.
2Productivity
If pitch and offset arrangements are optimized for performance, then device density improves, but manufacturing complexity increases
Solution Approach 1:
The patent incorporates alternating conductive layers and insulating layers in a predetermined stacked sequence before forming the memory openings. The conductive layers (containing materials such as tungsten, copper, or aluminum) and insulating layers (such as silicon dioxide or silicon nitride) are deposited in alternating fashion, creating a pre-structured template. Subsequent memory opening formation and filling operations then proceed more easily because the electrical isolation and connectivity pathways are already established by the alternating layer structure.
Solution Approach 2:
The patent implements a nested structure where memory openings are vertically stacked in columns, with each memory opening containing a fill structure that includes conductive material, semiconductor material, and insulating material in concentric or layered arrangements. The fill structures are nested within the openings, which are themselves nested within the alternating conductive and insulating layer stack. This nested configuration maximizes space utilization and achieves high device density while maintaining a systematic manufacturing approach.
Data Source
AI summary
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a plurality of periodic two-dimensional arrays of memory openings vertically extending through the alternating stack, a plurality of periodic two-dimensional arrays of memory opening fill structures, and bit lines. The bit lines laterally extend along a second horizontal direction. Each periodic two-dimensional array of memory openings includes a plurality of columns of memory openings in which neighboring columns of memory openings are laterally spaced apart along a first horizontal direction with an intercolumnar pitch. Memory openings within each column of memory openings are laterally spaced apart along the second horizontal direction with a nearest-neighbor pitch.