3D Memory Assembly Bonding for Higher Density Without Extreme Scaling

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Solution Overview

Problem

Planar memory cells face density limitations as feature sizes approach a lower limit, making scaling and fabrication challenging and costly, while 3D memory architectures offer a solution to increase memory density.

Innovation Solution

A 3D memory device is constructed by bonding two semiconductor assemblies with an inter-assembly bonding layer, each assembly comprising a memory stack and peripheral circuits, allowing for increased cell density without sacrificing cell size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If planar memory cells are scaled to smaller sizes to increase density, then memory density improves, but fabrication becomes challenging and costly

Engineering Contradiction:

Improvememory densityVSAvoidfabrication difficulty

Core Design Contradiction:

Quantity of substanceVSEase of manufacture

Solution Approach 1:

The patent transitions from planar (2D) memory cell architecture to three-dimensional stacked memory assemblies. Multiple semiconductor assemblies are bonded together vertically to form stacks, increasing memory density by utilizing the vertical dimension rather than continuing to scale lateral dimensions. This resolves the fabrication difficulty associated with extreme planar scaling while achieving higher density.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The memory device is divided into multiple separate semiconductor assemblies that are fabricated independently and then bonded together. Each assembly contains memory stacks and peripheral circuits that can be manufactured separately using standard processes, avoiding the need for complex single-chip fabrication. This segmentation enables modular manufacturing and simplifies the overall fabrication process.

Inventive Principle:

Principle #1Segmentation

2Quantity of substance

If multiple semiconductor assemblies are bonded together to form 3D memory device, then memory cell capacity per unit area increases, but manufacturing time and thermal damage increase

Engineering Contradiction:

Improvememory cell capacity per unit areaVSAvoidmanufacturing time

Core Design Contradiction:

Quantity of substanceVSLoss of time

Solution Approach 1:

Semiconductor assemblies are prepared in advance with bonding surfaces and associated structures (such as conductive vias and interconnects) formed before the bonding process. This preliminary preparation allows assemblies to be manufactured independently and stocked, reducing overall manufacturing time when final assembly is required. The bonding process itself is optimized to occur quickly at controlled conditions.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

A bonding layer or intermediary material is introduced at the bonding interfaces between semiconductor assemblies. This intermediary facilitates reliable electrical and mechanical connection while enabling the bonding process to occur under milder conditions, reducing thermal damage and allowing faster processing. The bonding layer acts as a mediator that simplifies the joining process.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Quantity of substance

If multiple semiconductor assemblies are bonded together to form 3D memory device, then memory cell capacity per unit area increases, but thermal damage increases

Engineering Contradiction:

Improvememory cell capacity per unit areaVSAvoidthermal damage

Core Design Contradiction:

Quantity of substanceVSObject-affected harmful factors

Solution Approach 1:

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The bonding process parameters are optimized to occur at lower temperatures and for shorter durations. By changing the thermal parameters of the bonding process (temperature, time, pressure), the patent achieves reliable assembly bonding while minimizing thermal damage to sensitive memory structures and peripheral circuits within the assemblies.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS20260040587A1Three-dimensional memory devices having semiconductor assemblies bonded by bonding layer and methods for forming the same

Publication Date: 2026.02.05 YANGTZE MEMORY TECH CO LTD

AI summary

Three-dimensional (3D) memory devices and methods for forming the same are disclosed. In certain aspects, a 3D memory device includes a first semiconductor assembly, a second semiconductor assembly, and an inter-assembly bonding layer between the first semiconductor assembly and the second semiconductor assembly. The first semiconductor assembly includes a first array structure and a first periphery structure. The first array structure includes a first memory stack having a plurality of interleaved stack conductive layers and stack dielectric layers. The first periphery structure includes a plurality of first peripheral circuits electrically connected to the first memory stack. The second semiconductor assembly includes a second array structure and a second periphery structure. The second array structure includes a second memory stack having a plurality of interleaved stack conductive layers and stack dielectric layers. The second periphery structure includes a plurality of second peripheral circuits electrically connected to the second memory stack.