3D Semiconductor Memory Asymmetric Vertical Patterns
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Solution Overview
Problem
Two-dimensional semiconductor devices face limitations in integration due to the high cost and practical limitations of expensive processing equipment needed for fine pattern formation, prompting the need for three-dimensional semiconductor memory devices with improved integration and structural stability.
Innovation Solution
The design includes a three-dimensional semiconductor memory device with a stacked electrode structure, lower and upper vertical patterns, and dummy structures, where the width of the lower patterns is greater than the upper patterns, providing increased pitch and stability during the formation of gate electrodes and electrode pads, thereby minimizing defects and enhancing integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional or planar semiconductor devices are used, then manufacturing cost is reduced, but integration is limited due to the practical limitations of expensive processing equipment needed for fine pattern formation
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional vertically stacked memory cells. This dimensional change allows multiple memory cells to be stacked above a single substrate area, dramatically increasing integration density without requiring proportionally more expensive fine-patterning equipment, thus resolving the contradiction between manufacturing cost and integration capability
2Stability of the object's composition
If the width of upper patterns is increased to improve stability, then structural stability improves, but the pitch between patterns increases, reducing integration density
Solution Approach 1:
The patent employs asymmetric width design where lower vertical patterns have greater width than upper vertical patterns. This asymmetric configuration provides enhanced structural stability and process margins during fabrication while maintaining compact pitch between patterns, thereby resolving the contradiction between structural stability and integration density
Data Source
AI summary
Disclosed are three-dimensional semiconductor memory devices including an electrode structure including gate electrodes stacked in a first direction, a lower pattern group including lower vertical patterns that are in a lower portion of the electrode structure and are connected to the substrate, and an upper pattern group including upper vertical patterns that are in an upper portion of the electrode structure. The upper vertical patterns may be connected to the lower vertical patterns, respectively. The devices may also include two common source plugs spaced apart from each other in a second direction. The electrode structure may be between the two common source plugs. An upper portion of the lower pattern group has a first width in the second direction, an upper portion of the upper pattern group has a second width in the second direction, and the first width may be greater than the second width.