3D Memory Cell Strings With Auxiliary Transistors
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Solution Overview
Problem
The operational reliability of semiconductor memory devices with a 3D memory cell array structure is compromised due to the increased complexity and potential for errors in data storage and retrieval.
Innovation Solution
The semiconductor memory device incorporates a memory cell array with cell strings and auxiliary strings coupled through a channel layer. The cell string has memory cells stacked along one side of the channel layer, while the auxiliary string comprises auxiliary transistors stacked along the opposite side. A voltage supply circuit applies specific voltages to unselected word lines and auxiliary word lines to optimize program and read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a 3D memory cell array structure is used to increase integration, then storage capacity is improved, but operational reliability deteriorates
Solution Approach 1:
The memory cell array is divided into multiple strings (first string, second string, third string, fourth string) with distinct word line connections. This segmentation allows independent control and verification of different data paths, reducing error propagation and improving operational reliability while maintaining high storage capacity through the 3D stacked structure
Solution Approach 2:
Different strings are configured with different word line connections (some connected to first word lines, others to second word lines). This local differentiation enables selective reading and verification of data through multiple paths, enhancing reliability by allowing cross-checking of stored data without compromising the integrated 3D structure
2Productivity
If multiple word lines are applied during program operation, then program speed is improved, but disturbance to unselected memory cells increases
Solution Approach 1:
Before applying the program voltage to the selected word line, pass voltages are preliminarily applied to all other word lines to ensure they are in a non-conductive state. This preliminary action prevents charge injection into unselected memory cells during the subsequent program operation, eliminating disturbance while maintaining fast programming through the selected word line
Solution Approach 2:
Different voltage parameters are applied to different word lines simultaneously: a high program voltage (e.g., 20V) is applied to the selected word line for fast programming, while lower pass voltages (e.g., 5V or 0V) are applied to unselected word lines to prevent disturbance. This parameter differentiation enables high-speed programming without affecting unselected memory cells
Data Source
AI summary
A semiconductor memory device includes a channel layer coupled to a bit line, a cell string located along a first side portion of the channel layer, and an auxiliary string located along a second side portion of the same channel layer.