3D Memory Cell Channel Pillar With Back Gate for Low-Voltage Operation

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Solution Overview

Problem

Three-dimensional semiconductor devices face challenges in operating memory cells effectively at low voltages due to the thinning of stacked material layers, making it difficult to maintain proper device operation.

Innovation Solution

The implementation of a memory cell structure with a back gate electrode and a channel pillar structure that includes a blocking layer, trap layer, tunneling layer, channel layer, and filling layer, allowing for the application of a back gate voltage to memory cells, which enables operation at lower voltages while maintaining device performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If the thickness of stacked material layers is reduced, then integration density is improved, but memory cell operation becomes difficult at low voltage

Engineering Contradiction:
Improvestacked material layers thicknessVSAvoidmemory cell operation
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

The gate structure is segmented into a front gate electrode and a back gate electrode, allowing independent control of channel potential. This segmentation enables proper memory cell operation at low voltages by applying back gate voltage to compensate for the reduced thickness of stacked material layers, thus resolving the contradiction between reduced thickness and reliable operation.

Inventive Principle:
Principle #1Segmentation

2Volume of moving object

If the thickness of stacked material layers is reduced, then integration density is improved, but operating voltage must be lowered

Engineering Contradiction:
Improvestacked material layers thicknessVSAvoidoperating voltage
Core Design Contradiction:
Volume of moving objectVSUse of energy by moving object

Solution Approach 1:

The gate structure is divided into front and back gate electrodes that can be independently controlled. The back gate electrode allows application of a voltage to maintain proper channel potential even when the stacked material layers are thin, enabling low-voltage operation while preserving integration density benefits.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

By introducing the back gate voltage as an additional control parameter, the system can maintain proper operating conditions with thinner stacked material layers. The back gate voltage compensates for the reduced thickness effect, allowing the device to operate at lower voltages without sacrificing performance.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If a back gate electrode is added, then memory cell operation at low voltage is enabled, but device complexity increases

Engineering Contradiction:
Improvememory cell operation at low voltageVSAvoidchannel structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The gate is segmented into front and back electrodes, which enables low-voltage operation through independent voltage control. While this adds structural elements, the segmentation allows for modular fabrication processes and independent optimization of each gate electrode, managing the complexity through systematic design.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The back gate electrode serves multiple functions: it enables low-voltage operation, provides additional control over channel potential, and can be used for threshold voltage adjustment. This multi-functionality justifies the added structural complexity by delivering multiple benefits from a single additional component.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution allows for the effective operation of memory cells at low voltages, enabling the thinning of word line stacks, increasing integration density, and improving the performance and capacity of three-dimensional semiconductor devices.

Implementation Method 1

a tunneling layer, a channel layer, a filling layer, and a back gate electrode. The channel structure may have a pillar shape.

Methodology Applied
Scientific EffectQuantum tunneling:

Data Source

PatentUS20240049467A1Three dimensional semiconductor device having a back-gate electrode
Publication Date: 2024.02.08 SK HYNIX INC
  • US20240049467A1 patent drawing
  • US20240049467A1 patent drawing
  • US20240049467A1 patent drawing

AI summary

A three dimensional semiconductor device is disclosed. The tree dimensional semiconductor device includes a word line stack over a substrate and a channel pillar structure passing through the word line stack in a vertical direction perpendicular to a top surface of the substrate. The channel pillar structure includes a channel structure. The channel structure includes a blocking layer, a trap layer, a tunneling layer, a channel layer, a filling layer, and a back gate electrode. The channel structure has a pillar shape.