3D Memory Array Back-Gate Biasing for Faster TFT Writes
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Solution Overview
Problem
Current semiconductor memory technologies, such as volatile RAM, face challenges in data retention and speed, particularly in write operations, as they lose information when powered off and have limited write speed and accuracy.
Innovation Solution
A three-dimensional memory array is developed using programmable thin film transistors (TFTs) with back gates, where the data storage layers are positioned between the back gates and word lines, allowing for increased write voltage during write operations by applying a biasing voltage to the back gate, enhancing write speed and accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional volatile RAM is used, then the memory device is simple in structure, but it loses information when powered off and has limited write speed and accuracy
Solution Approach 1:
The patent transitions from planar 2D memory architecture to three-dimensional vertically stacked memory structures. Multiple memory layers are stacked vertically with word lines extending through multiple layers, enabling non-volatile data storage while maintaining scalability and improving data retention without proportionally increasing device footprint complexity
Solution Approach 2:
The patent employs composite material structures including ferroelectric materials for non-volatile data storage, combined with conventional semiconductor materials. This composite approach enables simultaneous achievement of non-volatility, fast write/read speeds, and improved reliability while managing structural complexity through material-level integration
2Productivity
If conventional memory write operations are used, then the process is simple, but the write speed and accuracy are limited
Solution Approach 1:
The patent segments the gate structure into front gate and back gate components, with data storage layers positioned between them. This segmentation enables independent voltage control of each gate, allowing the back gate to provide additional write voltage boost without proportionally increasing total energy consumption, thereby improving write speed while managing energy use
Solution Approach 2:
The patent changes the electrical parameter configuration by applying biasing voltages to the back gate during write operations. This parameter change enables dynamic adjustment of the electric field across the data storage layer, increasing write voltage and improving write speed and accuracy without requiring proportional increases in overall system energy consumption
3Measurement precision
If data storage layers are positioned between back gates and word lines, then write voltage is increased improving write speed and accuracy, but the decoder complexity is reduced
Solution Approach 1:
The patent uses vertical stacking of multiple memory layers with word lines extending through multiple layers in the vertical dimension. This three-dimensional arrangement allows shared word lines to access multiple layers, reducing the number of required decoders and their complexity while maintaining high write accuracy through the enhanced electric field from the back gate configuration
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the performance of the memory array by increasing write speed and accuracy while reducing the complexity of the row and column decoders, and allows for faster and more reliable data storage.
Implementation Method 1
a biasing voltage is applied to the back gate of the TFT, thereby increasing the write voltage applied across the data storage layer of the TFT during the write operation
Data Source
AI summary
In an embodiment, a device includes: a source line extending in a first direction; a bit line extending in the first direction; a back gate between the source line and the bit line, the back gate extending in the first direction; a channel layer surrounding the back gate; a word line extending in a second direction, the second direction perpendicular to the first direction; and a data storage layer extending along the word line, the data storage layer between the word line and the channel layer, the data storage layer between the word line and the bit line, the data storage layer between the word line and the source line.