3D Memory Array Back-Gate Layout for Channel Surface Potential Control
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Solution Overview
Problem
Current semiconductor memory technologies face challenges in enhancing the performance and density of memory arrays, particularly in controlling the surface potential of channel layers during write operations, which affects the efficiency and reliability of data storage in three-dimensional memory devices.
Innovation Solution
A three-dimensional memory array is designed with programmable thin film transistors (TFTs) having source lines and bit lines with extension regions acting as back gates, where the data storage layers and channel layers are positioned between the back gates and word lines, allowing for controlled surface potential reduction during write operations, thereby improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional memory structures are used, then device density is limited, but write operation efficiency and surface potential control are insufficient
Solution Approach 1:
The patent transitions from planar memory structures to three-dimensional stacked structures with multiple layers. Word lines, bit lines, and channel layers are arranged in vertical stacks, enabling increased device density while providing multiple access paths for write operations. This dimensional change allows simultaneous control of surface potential through extension regions in the vertical dimension.
Solution Approach 2:
The memory array is divided into multiple stacked layers with individual word lines, bit lines, and channel layers in each layer. Each layer can be independently controlled through its own word line and extension regions, allowing precise surface potential management for each segment while maintaining high overall density.
2Productivity
If device density is increased through three-dimensional stacking, then productivity improves, but control of surface potential during write operations becomes more difficult
Solution Approach 1:
Extension regions are introduced as intermediary structures between the bit lines and channel layers. These extension regions act as back gates that mediate the control of surface potential in the channel layers during write operations. The extension regions provide an additional control interface that simplifies the management of surface potential in complex three-dimensional structures.
Solution Approach 2:
The extension regions function as feedback control elements by allowing adjustment of surface potential based on the state of the channel layer. During write operations, the extension regions can be programmed to maintain appropriate surface potential levels, providing automatic feedback control that simplifies the overall write process in high-density three-dimensional structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the write operation efficiency by reducing surface potential, increasing write voltage, and improving the overall performance of the memory array, leading to increased device density and reliability.
Implementation Method 1
controlling the surface potential of channel layers during write operations, which affects the efficiency and reliability of data storage
Implementation Method 2
data storage layers and channel layers are positioned between the back gates and word lines for the transistors
Data Source
AI summary
In an embodiment, a device includes: a word line extending in a first direction; a data storage layer on a sidewall of the word line; a channel layer on a sidewall of the data storage layer; a back gate isolator on a sidewall of the channel layer; and a bit line having a first main region and a first extension region, the first main region contacting the channel layer, the first extension region separated from the channel layer by the back gate isolator, the bit line extending in a second direction, the second direction perpendicular to the first direction.