3D Memory Programming via Back-Gate Verification
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Solution Overview
Problem
Three-dimensional semiconductor memory devices face challenges in operating speeds and introducing disturbances due to significant voltage disparities between selected and non-selected word lines and bit lines during programming and reading operations.
Innovation Solution
A method is provided for programming and reading three-dimensional semiconductor memory devices, involving specific voltage applications to word lines, bit lines, and back-gate electrodes, including multiple programming and verification steps with varying voltages to optimize operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If significant voltage disparities are applied between selected and non-selected word lines and bit lines during programming and reading operations, then the memory device can perform basic read and write functions, but the operating speed decreases and various disturbances are introduced
Solution Approach 1:
The patent applies multiple verification voltages with different magnitudes to the back-gate electrode during programming and reading operations. By dynamically changing the voltage parameter applied to the back-gate electrode, the system can reduce voltage disparities between selected and non-selected lines, thereby reducing data disturbance while maintaining operating speed. The verification voltages are specifically designed to be lower than traditional single verification voltages, enabling faster operations with reduced interference.
2Measurement precision
If a single verification voltage is applied to the back-gate electrode, then the verification process is simple, but the accuracy of threshold voltage distribution verification is insufficient
Solution Approach 1:
The patent segments the verification process into multiple steps, each with different verification voltages applied to the back-gate electrode. Instead of using a single verification voltage, the system applies a first verification voltage and a second verification voltage sequentially, allowing for comprehensive verification of the threshold voltage distribution. This segmentation enables accurate measurement of different regions in the threshold voltage distribution without significantly increasing overall process complexity.
Solution Approach 2:
The patent employs dynamic voltage application during verification operations. The verification voltages are applied dynamically based on the specific verification step being performed, with the system adapting the voltage magnitude and timing to optimize verification accuracy. This dynamic approach allows the system to achieve high measurement precision while maintaining efficient operation by applying voltages only when and where needed.
3Reliability
If high word line programming voltages are used to ensure programming accuracy, then programming reliability is improved, but the voltage disparity with non-selected word lines increases, causing more disturbances
Solution Approach 1:
The back-gate electrode serves as an intermediary element that mediates the voltage disparity between selected and non-selected word lines. By applying verification voltages to the back-gate electrode, the system creates an intermediate voltage level that reduces the direct voltage disparity between word lines and bit lines during programming operations. This intermediary approach allows high programming voltages to be used for accuracy while minimizing the harmful voltage disparities that cause disturbances in non-selected cells.
Data Source
AI summary
A method of programming a three-dimensional semiconductor memory device includes applying a first word line programming voltage to a selected word line among the word lines, floating unselected word lines among the word lines, and applying a back-gate pass voltage to the back-gate electrode; applying a first word line verification voltage to the selected word line, applying a word line pass voltage to the unselected word lines, and applying a first back-gate verification voltage to the back-gate electrode; applying a second word line programming voltage to the selected word line, floating the unselected word lines, and applying the back-gate pass voltage to the back-gate electrode; and applying a second word line verification voltage to the selected word line, applying the word line pass voltage to the unselected word lines, and applying a second back-gate verification voltage to the back-gate electrode.