3D Semiconductor Memory Layout With Backside Capacitor Integration
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Solution Overview
Problem
There is a need for semiconductor memory devices with increased data storage capacity and reduced size, as conventional two-dimensional memory cells are insufficient for meeting the growing demands of electronic systems.
Innovation Solution
The semiconductor memory device incorporates a peripheral circuit structure and a cell structure, where the cell structure is stacked on the peripheral circuit structure. The peripheral circuit structure includes a peripheral circuit board with capacitors and wiring lines, and the cell structure includes memory cells and gate electrodes, allowing for a compact and efficient design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged two-dimensionally, then device structure is simple and manufacturing is easy, but data storage capacity is limited
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional stacked structure. Multiple memory cell layers are stacked vertically on the peripheral circuit board, enabling increased storage capacity by utilizing the vertical dimension while maintaining compatibility with existing manufacturing processes
2Quantity of substance
If memory cells are arranged three-dimensionally, then data storage capacity increases, but device size increases
Solution Approach 1:
The patent integrates the capacitor structure directly into the peripheral circuit board, merging the capacitor function with the substrate. This eliminates the need for separate capacitor components and reduces overall device volume while maintaining high storage capacity through vertical stacking
3Ease of manufacture
If capacitors are placed on the same side as circuit elements, then wiring is simple, but device area increases
Solution Approach 1:
The patent places capacitors on the back side of the peripheral circuit board, opposite to the circuit elements. This vertical separation in the third dimension eliminates area conflict while maintaining simple wiring through through-silicon vias or conductive layers that penetrate the substrate
Data Source
AI summary
A semiconductor memory device includes a peripheral circuit structure; and a cell structure including a cell substrate and a gate electrode, on the peripheral circuit structure. The peripheral circuit structure includes a peripheral circuit board including a first surface facing the cell structure and a second surface opposite to the first surface, a first circuit element on the first surface of the peripheral circuit board, a first wiring line electrically connected to the first circuit element in a first interlayer insulating layer, a capacitor dielectric layer covering the second surface of the peripheral circuit board, a first capacitor electrode in the capacitor dielectric layer, a second capacitor electrode spaced apart from the first capacitor electrode in the capacitor dielectric layer, and a first connection via electrically connecting the first capacitor electrode with the first wiring line by passing through the peripheral circuit board.