3D Memory Backside Source Contact for Lower Leakage and Higher Yield
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Solution Overview
Problem
The existing 3D NAND memory devices face challenges with front side source contacts, which introduce leakage current and parasitic capacitance, complicate the fabrication process, and reduce production yield due to issues like overlay control and epitaxial layer formation, especially as the number of levels increases.
Innovation Solution
The implementation of backside source contacts in 3D memory devices eliminates the need for front side source contacts, reducing leakage current and parasitic capacitance, and replaces bottom semiconductor plugs with N-wells for gate-induce-drain-leakage-assisted body biasing, simplifying the fabrication process and increasing yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If front side source contacts are used in 3D NAND memory devices, then electrical connection is achieved, but leakage current and parasitic capacitance increase
Solution Approach 1:
The patent inverts the conventional location of source contacts from the front side to the back side of the memory device. By forming source contacts on the back side of the substrate rather than on the front side, the patent eliminates the harmful interactions between front-side source contacts and channel structures, thereby reducing leakage current and parasitic capacitance while maintaining electrical connection functionality
2Reliability
If front side source contacts are used, then electrical connection is established, but fabrication process complexity increases
Solution Approach 1:
The patent simplifies the fabrication process by inverting the source contact location to the back side, which eliminates the need for complex overlay control and epitaxial layer formation processes that are required when using front side source contacts in high-level 3D NAND structures
3Reliability
If front side source contacts are used, then electrical connection is achieved, but production yield decreases
Solution Approach 1:
By moving source contacts to the back side, the patent avoids fabrication challenges such as overlay control and epitaxial layer formation that become increasingly difficult as the number of levels increases, thereby improving production yield while maintaining electrical connection reliability
4Reliability
If bottom semiconductor plugs are used, then source contact formation is achieved, but overlay control and epitaxial layer formation issues arise
Solution Approach 1:
The patent replaces bottom semiconductor plugs with back-side source contacts formed through the substrate. This inversion eliminates the need for precise overlay control and epitaxial layer formation at the bottom of the structure, as source contacts are now formed on the accessible back side where standard fabrication processes can be applied
Solution Approach 2:
The patent extracts the source contact formation process from the bottom of the channel structures and relocates it to the back side of the substrate. This separation removes the problematic bottom plug formation step that causes overlay and epitaxial layer issues, while still achieving the necessary electrical connection function
Data Source
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AI summary
Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a peripheral circuit on the substrate, a memory stack including interleaved conductive layers and dielectric layers above the peripheral circuit, a first semiconductor layer above the memory stack, a second semiconductor layer above and in contact with the first semiconductor layer, a plurality of channel structures each extending vertically through the memory stack and the first semiconductor layer, and a source contact above the memory stack and in contact with the second semiconductor layer.