3D Memory Backside Source Contacts for Slit-Free Plug Formation
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Solution Overview
Problem
The existing 3D NAND memory devices face challenges with front side source contacts, which introduce leakage current and parasitic capacitance, and the formation of sidewall semiconductor plugs is complicated by increasing aspect ratios, leading to higher costs and reduced yield due to the need for deposition and etching through slit openings.
Innovation Solution
The solution involves moving source contacts to the backside, allowing for the formation of sidewall semiconductor plugs without the need for deposition or etching through the stack structure, thereby reducing fabrication complexity and cost, and improving scalability by avoiding the aspect ratio limitations of the slit openings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If front side source contacts are used in 3D NAND memory devices, then the memory device can be formed with conventional architecture, but leakage current and parasitic capacitance are introduced
Solution Approach 1:
The patent inverts the conventional front-side source contact architecture by moving the source contacts to the backside of the memory device. This inversion eliminates the harmful leakage current and parasitic capacitance associated with front-side contacts while maintaining the necessary electrical connectivity through the substrate.
2Reliability
If sidewall semiconductor plugs are formed through slit openings in the stack structure, then electrical connections can be established, but the increasing aspect ratio leads to higher fabrication complexity and cost
Solution Approach 1:
The patent extracts the source contact formation process from the constrained slit opening environment and relocates it to the backside of the substrate. This extraction eliminates the aspect ratio limitations imposed by the slit openings, allowing for simpler plug formation with reduced fabrication complexity and lower costs.
3Productivity
If deposition and etching are performed through slit openings to form sidewall semiconductor plugs, then the memory device can be assembled, but yield is reduced due to process limitations
Solution Approach 1:
The patent inverts the process sequence by forming source contacts through the backside substrate rather than through the slit openings in the stack. This inversion avoids the yield-reducing limitations of deposition and etching through narrow slits, enabling higher manufacturing yield while still achieving complete device assembly.
Data Source
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Figure 3A~3B
AI summary
Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A sacrificial layer on a substrate, a P-type doped semiconductor layer having an N-well on the sacrificial layer, and a dielectric stack on the P-type doped semiconductor layer are subsequently formed. A channel structure extending vertically through the dielectric stack and the P-type doped semiconductor layer is formed. The dielectric stack is replaced with a memory stack, such that the channel structure extends vertically through the memory stack and the P-type doped semiconductor layer. The substrate and the sacrificial layer are removed to expose an end of the channel structure. Part of the channel structure abutting the P-type doped semiconductor layer is replaced with a semiconductor plug.