3D Memory Backside Interconnect Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
Planar memory cell technologies face challenges in scaling due to feature size limitations, leading to increased costs and density constraints, which 3D memory architecture aims to address by optimizing backside interconnect structures to enhance memory cell density and reduce leakage current and parasitic capacitance.
Innovation Solution
The implementation of backside interconnect structures, including a source line mesh and power line mesh, on the 3D memory device, which relocates source lines and power lines from the front side to the backside of the memory array substrate, optimizing metal routings and reducing resistance, and utilizing through-silicon contacts to connect peripheral circuits to the memory array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cell scaling is pursued to increase density, then memory density improves, but feature size approaches lower limit causing process challenges and increased cost
Solution Approach 1:
The patent transitions from planar 2D memory cell architecture to 3D vertical architecture by stacking multiple memory layers above a substrate. Memory stacks extend vertically with alternating conductive and dielectric layers, enabling increased storage density without further reducing lateral feature sizes. This dimensional transition resolves the scaling limitation by exploiting the third dimension for capacity expansion.
2Reliability
If source lines and power lines are routed on the front side of the memory array substrate, then connection is achieved, but resistance increases and parasitic capacitance is generated
Solution Approach 1:
The patent inverts the conventional interconnect architecture by relocating source lines and power lines from the front side to the back side of the memory array substrate. Through-silicon vias (TSVs) are formed to penetrate the substrate and connect backside interconnect layers to front-side memory stacks. This inversion reduces parasitic capacitance between source lines and memory cells, minimizes leakage current, and lowers overall resistance by optimizing current paths.
3Reliability
If backside interconnect structures are implemented, then resistance is reduced and parasitic capacitance is minimized, but device complexity increases
Solution Approach 1:
The patent segments the interconnect structure into distinct front-side and back-side components. Front-side elements include memory stacks and bit line contacts, while back-side elements include source lines, power lines, and control circuitries. Through-silicon vias serve as vertical interconnect segments linking the two sides. This segmentation allows independent optimization of each interconnect layer, simplifying manufacturing processes despite the overall 3D complexity.
Data Source
AI summary
Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including interleaved conductive layers and dielectric layers above the substrate, a plurality of channel structures each extending vertically through the memory stack, a semiconductor layer above and in contact with the plurality of channel structures, a plurality of source contacts above the memory stack and in contact with the semiconductor layer, a plurality of contacts through the semiconductor layer, and a backside interconnect layer above the semiconductor layer including a source line mesh in a plan view. The plurality of source contacts are distributed below and in contact with the source line mesh. A first set of the plurality of contacts are distributed below and in contact with the source line mesh.