3D Memory Backside Insulating Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
Conventional 3D memory devices face challenges with parasitic capacitance, leading to slow ramping and high current consumption during memory erase and program operations due to wall-type array common source (ACS) contacts and large PN-wells that span across memory blocks.
Innovation Solution
The implementation of backside source line contacts and trench isolations to reduce parasitic capacitance, with slit structures filled with dielectric materials and PN-wells split into multiple blocks for individual control, thereby minimizing coupling capacitance and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If wall-type array common source (ACS) contacts and large PN-wells are used to span across memory blocks, then structural simplicity is maintained, but parasitic capacitance increases leading to slow ramping and high current consumption
Solution Approach 1:
The patent divides the continuous PN-well into multiple separate PN-wells, with each PN-well corresponding to a specific memory block. This segmentation eliminates the large parasitic capacitance associated with a single continuous PN-well spanning multiple blocks, thereby reducing current consumption during erase and program operations while maintaining structural simplicity through the modular arrangement.
2Ease of manufacture
If wall-type array common source (ACS) contacts are used, then ease of manufacture is improved, but parasitic capacitance causes slow word line bias ramping speed
Solution Approach 1:
The patent segments the continuous ACS contact structure into block-specific contacts, where each memory block has its own dedicated contact. This segmentation reduces the parasitic capacitance that limits ramping speed in conventional wall-type structures, enabling faster word line bias ramping while maintaining ease of manufacture through standardized fabrication processes.
3Device complexity
If large PN-wells spanning across memory blocks are used, then device complexity is reduced, but power consumption increases due to parasitic capacitance
Solution Approach 1:
The patent divides the single large PN-well into multiple smaller PN-wells, each associated with a specific memory block. This segmentation eliminates the excessive parasitic capacitance of the large continuous PN-well, thereby reducing power consumption during memory operations while keeping device complexity low through the systematic repetition of standardized block structures.
Solution Approach 2:
The patent implements local control of PN-well voltage for each memory block, allowing independent voltage adjustment tailored to the specific needs of each block. This local quality approach optimizes power consumption by applying voltage only where and when needed, rather than uniformly across all blocks, thereby reducing overall power loss while maintaining manageable device complexity.
Data Source
AI summary
Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate having a first side and a second side opposite to the first side. The 3D memory device also includes a memory stack including interleaved conductive layers and dielectric layers at the first side of the substrate. The 3D memory device also includes a plurality of channel structures each extending vertically through the memory stack. The 3D memory device also includes a slit structure extending vertically through the memory stack and extending laterally to separate the plurality of channel structures into a plurality of blocks. The 3D memory device further includes a first doped region in the substrate and in contact with the slit structure. The 3D memory device further includes an insulating structure extending vertically from the second side of the substrate to the first doped region. The 3D memory device further includes a plurality of second doped regions in the substrate and separated by the insulating structure.