3D Memory Backside Interconnect Layout for Lower Routing Resistance
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Solution Overview
Problem
Planar memory cells face density limitations as feature sizes approach a lower limit, making scaling and fabrication costly, and existing 3D memory devices waste backside area with inefficient metal routings.
Innovation Solution
Implement a 3D memory device with backside interconnect structures, including a source line mesh and power line mesh on the backside of the memory array substrate, optimizing metal routings and reducing resistance by moving source lines and power lines from the front side to the backside.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology, then memory density is improved, but manufacturing cost and fabrication difficulty increase significantly
Solution Approach 1:
The patent transitions from planar 2D memory cell architecture to three-dimensional stacked architecture. Multiple memory stacks are formed vertically on the substrate, with word lines extending in first directions and bit lines in second directions perpendicular to the word lines. This 3D configuration enables continued memory density scaling without requiring further reduction of planar feature sizes, thereby avoiding the associated manufacturing complexity and cost increases.
2Area of stationary object
If metal routings are placed on the front side of the memory array substrate, then connection is achieved, but backside area is wasted and resistance is high
Solution Approach 1:
The patent relocates metal routings from the front side to the backside of the memory array substrate. Word lines extend from the front side through the substrate to the back side, where they are connected to bit lines formed on the backside surface. This configuration utilizes the previously wasted backside area for electrical connections, reduces the path length and resistance of metal routings, and improves overall electrical performance while enabling higher memory cell density on the front side.
3Quantity of substance
If feature sizes of memory cells are reduced to increase density, then memory capacity is improved, but leakage current and parasitic capacitance increase
Solution Approach 1:
The patent employs three-dimensional stacked memory architecture where memory cells are arranged vertically in multiple stacks. This approach increases memory capacity by utilizing the vertical dimension rather than continuously reducing planar feature sizes. By maintaining larger feature sizes in the 3D architecture, the patent reduces leakage current and parasitic capacitance that would otherwise result from extreme miniaturization, while still achieving high memory capacity through increased vertical stacking.
Data Source
AI summary
In an example, a three-dimensional (3D) memory device includes a memory stack including interleaved conductive layers and dielectric layers, a channel structure extending vertically through the memory stack, a semiconductor layer over the memory stack and electrically connected to the channel structure, and a source contact over the memory stack and electrically connected to the semiconductor layer. The source contact and the memory stack are disposed on opposite sides of the semiconductor layer.