3D Memory Backside Source Contact Layout for Leakage Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Planar memory cells face density limitations and fabrication challenges as feature sizes approach a lower limit, leading to increased costs and complexity, while existing 3D memory devices suffer from issues like leakage current, parasitic capacitance, and fabrication complications due to front side source contacts and semiconductor plugs.
Innovation Solution
The implementation of backside source contacts in 3D memory devices, eliminating front side source contacts and semiconductor plugs, which reduces cell area requirements, avoids leakage current and parasitic capacitance, and simplifies the fabrication process by eliminating spacer formation and issues related to bottom semiconductor plugs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If front side source contacts and semiconductor plugs are used in 3D memory devices, then electrical connection is achieved, but leakage current and parasitic capacitance increase
Solution Approach 1:
The patent inverts the conventional location of source contacts from the front side to the back side of the 3D memory device. By forming source contacts on the backside substrate surface rather than on the front side, the patent eliminates the harmful effects of front-side source contacts including leakage current and parasitic capacitance, while maintaining necessary electrical connections through the substrate
2Reliability
If front side source contacts are used, then electrical connection is achieved, but cell area increases
Solution Approach 1:
The patent moves the source contacts from the two-dimensional front side surface to the back side surface of the substrate, utilizing the third dimension (depth/vertical arrangement) to resolve the area conflict. This dimensional relocation allows front-side cell area to be minimized while back-side source contacts provide necessary electrical connections
3Reliability
If semiconductor plugs are used for bottom contacts, then electrical connection is achieved, but fabrication complexity increases
Solution Approach 1:
The patent extracts and removes the semiconductor plugs from the device structure, eliminating the need for complex plug formation processes including spacer deposition and pattern transfer. The source contacts are directly formed on the backside substrate surface without requiring intermediate plug structures, thereby simplifying the fabrication process
4Productivity
If planar memory cell scaling continues, then memory density increases, but fabrication challenges and costs increase
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell scaling to three-dimensional vertical stacking architecture. By arranging memory cells in vertical stacks with multiple levels separated by interlevel dielectric layers, the patent achieves high memory density without further reducing feature sizes, thereby avoiding the fabrication challenges and costs associated with continued planar scaling
Data Source
Figure 1
Figure 2A
Figure 2B
AI summary
Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A sacrificial layer above a second semiconductor layer at a first side of a substrate and a dielectric stack on the sacrificial layer are subsequently formed. A channel structure extending vertically through the dielectric stack and the sacrificial layer into the second semiconductor layer is formed. The sacrificial layer is replaced with a first semiconductor layer in contact with the second semiconductor layer. The dielectric stack is replaced with a memory stack, such that the channel structure extends vertically through the memory stack and the first semiconductor layer into the second semiconductor layer. A source contact is formed at a second side opposite to the first side of the substrate to be in contact with the second semiconductor layer.