3D Memory Backside Source Contact Layout for Lower Leakage
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Solution Overview
Problem
Planar memory cells face density limitations and fabrication challenges as feature sizes approach a lower limit, leading to increased costs and reduced production yield due to issues like leakage current, parasitic capacitance, and local stress from front side slit structures and bottom semiconductor plugs.
Innovation Solution
A 3D memory device with backside source contacts is implemented, eliminating front side source contacts and replacing bottom semiconductor plugs with N-wells, which reduces leakage current and parasitic capacitance, and simplifies the fabrication process by avoiding issues like overlay control and epitaxial layer formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If front side source contacts and bottom semiconductor plugs are used in planar memory cells, then electrical connectivity is achieved, but leakage current and parasitic capacitance increase
Solution Approach 1:
The patent inverts the conventional location of source contacts from the front side to the back side of the memory device. By forming source contacts on the back side surface that extend into the substrate, the patent eliminates the need for front side source contacts and bottom semiconductor plugs, thereby reducing leakage current and parasitic capacitance while maintaining electrical connectivity.
2Quantity of substance
If feature sizes of planar memory cells are reduced to increase density, then memory cell density improves, but fabrication complexity and cost increase
Solution Approach 1:
The patent transitions from a conventional planar architecture to a three-dimensional architecture by moving source contacts to the back side surface and forming them to extend vertically into the substrate. This dimensional change allows for increased memory cell density without proportionally increasing fabrication complexity, as the back side source contacts can be formed using standard semiconductor processing techniques.
3Reliability
If bottom semiconductor plugs are used for electrical connection, then connectivity is established, but manufacturing precision requirements increase due to overlay control and epitaxial layer formation
Solution Approach 1:
The patent extracts and eliminates the bottom semiconductor plugs from the conventional memory cell structure. By forming source contacts directly on the back side surface that extend into the substrate, the patent removes the need for precise overlay control and epitaxial layer formation required for bottom semiconductor plugs, thereby reducing manufacturing precision requirements while maintaining electrical connection.
Data Source
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AI summary
Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a peripheral circuit on the substrate, a memory stack including interleaved conductive layers and dielectric layers above the peripheral circuit, a first semiconductor layer above the memory stack, a second semiconductor layer above and in contact with the first semiconductor layer, a plurality of channel structures each extending vertically through the memory stack and the first semiconductor layer, and a source contact above the memory stack and in contact with the second semiconductor layer.