3D Memory Wafer Bonding With Balanced Word Line Loads
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Solution Overview
Problem
Existing 3D memory architectures face issues with unbalanced loads at the ends of word lines during bonding, leading to abnormal bonding and metal voids due to electrochemical reactions, resulting in packaging failures and economic losses.
Innovation Solution
A balanced load configuration is implemented by connecting both ends of the structure to be tested with symmetrical circuit arrangements through peripheral wafer jumpers, ensuring equal electrochemical reactions and reducing metal voids.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional 3D memory bonding is performed without balanced load configuration, then bonding process can be completed, but unbalanced loads at word line ends cause abnormal bonding and metal voids due to electrochemical reactions
Solution Approach 1:
The patent applies asymmetry by introducing different circuit configurations at the two ends of the word line. Specifically, one end is connected to a peripheral circuit while the other end is left unconnected or connected to a different circuit element, creating an asymmetric load distribution that balances the electrochemical reactions during bonding and prevents metal void formation.
Solution Approach 2:
The patent implements equipotentiality by ensuring that both ends of the word line are at equal electrochemical potential during the bonding process. This is achieved through the balanced load configuration where symmetric circuit elements are connected to both ends, equalizing the electrical conditions and preventing differential electrochemical reactions that would otherwise create metal voids.
2Reliability
If balanced load configuration is implemented with symmetrical circuit arrangements, then metal voids are reduced, but device complexity increases due to additional peripheral wafer jumpers and circuit connections
Solution Approach 1:
The patent applies segmentation by dividing the bonding structure into separate modular components: peripheral wafer jumpers, peripheral circuits, and array wafer elements. This modular approach allows the balanced load configuration to be implemented as discrete, manageable segments rather than a monolithic complex structure, facilitating easier fabrication and testing.
Solution Approach 2:
The patent implements universality by designing the peripheral wafer jumpers and contact blocks to serve multiple functions: they provide electrical connections for the balanced load configuration, serve as bonding interfaces, and enable both testing and operational modes. This multi-functionality reduces the need for separate dedicated structures, thereby limiting the increase in device complexity.
3Reliability
If peripheral wafer jumpers are used to connect both ends of structure to be tested, then packaging failures are minimized, but manufacturing precision requirements increase due to alignment demands
Solution Approach 1:
The patent applies preliminary action by pre-configuring the peripheral wafer with jumpers and contact blocks before the bonding process. The balanced load circuit elements are installed and positioned in advance, allowing for preliminary testing and adjustment. This pre-preparation ensures that when bonding occurs, the alignment requirements are already optimized, reducing the actual manufacturing precision demands during the critical bonding step.
Solution Approach 2:
The patent introduces peripheral wafer contact blocks as intermediary elements between the peripheral wafer jumpers and the array wafer bonding contacts. These contact blocks serve as mediators that facilitate alignment and connection, providing a buffer zone that reduces the direct alignment precision requirements between the peripheral and array wafers during bonding.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances bonding reliability by minimizing metal voids and packaging failures, improving the overall yield and reducing economic losses.
Implementation Method 1
After the two wafers have been prepared, they can be bonded together such that the bonded array wafer and peripheral wafer are connected to each other through corresponding bonding contacts
Implementation Method 2
unbalanced loads at the ends of word lines during bonding, leading to abnormal bonding and metal voids due to electrochemical reactions
Data Source
AI summary
The present disclosure discloses a three-dimensional (3D) memory, which includes a peripheral wafer and an array wafer. The peripheral wafer includes a first peripheral structure and a second peripheral structure. The array wafer includes a substrate, a structure to be tested and multiple interconnecting portions. The substrate includes a first well region and a second well region. The array wafer includes the structure to be tested which has a first connecting portion, a second connecting portion, and multiple interconnecting portions. The first peripheral structure is connected to the first well region and the first connecting portion of the structure to be tested by the first interconnecting portion and the second interconnecting portion respectively. The second peripheral structure is connected to the second well region and the second connecting portion of the structure to be tested by the third interconnecting portion and the fourth interconnecting portion respectively.