3D Memory Interconnect Barrier Structure for Insulation Reliability
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Solution Overview
Problem
There is a demand for semiconductor devices capable of storing high-capacity data, and existing technologies have not effectively addressed the need for increased data storage capacity while maintaining reliability.
Innovation Solution
A semiconductor device design incorporating a lower structure with memory cells and peripheral circuits, an upper structure with inter-metal insulating layers, conductive vias, and conductive patterns, including specific barrier structures to enhance electrical insulation and connectivity, is proposed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensionally arranged memory cells are used to increase data storage capacity, then storage capacity is improved, but device complexity increases
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional arrangement, stacking memory cells vertically to increase storage capacity without expanding planar area. This dimensional change enables higher density storage while managing complexity through systematic layering and standardized interconnection structures.
Solution Approach 2:
The memory device is divided into multiple stacked layers including memory cell layers, inter-metal insulating layers, and conductive via structures. Each layer performs a specific function, allowing independent optimization and simplifying the overall complex structure through modular segmentation of the three-dimensional architecture.
2Reliability
If barrier structures are added to enhance electrical insulation, then reliability is improved, but device complexity increases
Solution Approach 1:
Barrier structures are introduced as intermediary elements between conductive components such as between the input/output interconnection line and the upper conductive via. These barrier structures provide electrical insulation and prevent unwanted current paths, enhancing reliability by acting as mediating elements that isolate conductive regions while integrating seamlessly into the existing architecture.
Solution Approach 2:
The barrier structures utilize composite material configurations combining insulating materials with conductive materials in layered arrangements. This composite approach provides effective electrical insulation while maintaining structural integrity and compatibility with surrounding conductive elements, improving reliability without requiring completely separate structural systems.
Data Source
AI summary
A semiconductor device includes a lower structure and an upper structure. The upper structure includes an inter-metal insulating layer, a first upper conductive via, upper conductive patterns, and a capping insulating structure. The upper conductive patterns include a first input/output interconnection line and a first barrier structure. The first input/output interconnection line includes a first connection region and a first pad region. The first connection region includes a first side surface, a second side surface, and a third side surface that extends from ends of the first side surface and the second side surface. The first barrier structure includes a first internal barrier structure and an external barrier structure. The first internal barrier structure includes a first internal line portion, a second internal line portion, and a third internal portion.