3D Memory Cell Structure With Conductive Base Layer Isolation
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Solution Overview
Problem
Current semiconductor devices face limitations in integration and performance due to the challenges in micropattern formation technology, which requires expensive equipment and restricts the integration of two-dimensional semiconductor devices.
Innovation Solution
A semiconductor device with a peripheral circuit structure and a cell structure that includes gate electrodes, a channel structure, a stack insulating layer, plugs, a conductive base layer, and a cover insulating layer, arranged in a specific configuration to enhance electrical characteristics and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If two-dimensional planar semiconductor devices are used to increase integration, then area occupancy is reduced, but manufacturing cost increases due to expensive micropattern formation equipment
Solution Approach 1:
The patent transitions from two-dimensional planar devices to three-dimensional vertically stacked devices. Multiple memory cell layers are stacked in the vertical direction, allowing high integration without requiring advanced micropattern formation technology. This dimensional change enables cost-effective manufacturing while achieving high density.
2Ease of manufacture
If peripheral circuit transistors are placed in the same plane as memory cells, then manufacturing is simplified, but electrical interference and reliability decrease
Solution Approach 1:
The patent separates peripheral circuits from memory cells by placing them in different vertical layers. Peripheral circuit transistors are positioned in a lower layer while memory cells are in upper layers, reducing electrical interference and improving reliability while maintaining manufacturing simplicity through the stacked architecture.
Solution Approach 2:
The patent divides the semiconductor device into distinct functional regions: a peripheral circuit region and a memory cell region. This segmentation allows independent optimization of each region while reducing mutual interference, with peripheral circuits at the bottom and memory cells stacked above.
3Quantity of substance
If more memory cell layers are stacked to increase capacity, then data storage capacity increases, but electrical characteristics and reliability may deteriorate
Solution Approach 1:
The patent introduces a conductive base layer specifically in the outer region of each memory cell layer, while the inner region maintains the stack insulating layer. This local differentiation provides electrical stabilization at critical outer regions without compromising the overall stacked structure, enabling high capacity with maintained reliability.
Solution Approach 2:
The patent uses a composite insulating layer structure combining stack insulating layer and cover insulating layer with different thicknesses and materials. This composite structure provides both mechanical support for multiple stacked layers and electrical isolation, enabling high-density stacking while maintaining electrical characteristics.
Data Source
AI summary
A semiconductor device includes a cell structure including a cell region, a connection region, and a peripheral circuit connection region, wherein the peripheral circuit connection region includes an inner region and an outer region surrounding the inner region, and the cell structure includes a plug passing through a stack insulating layer in the inner region, a conductive base layer spaced apart from the plug in a horizontal direction in the outer region, a cover insulating layer located on an upper surface of the conductive base layer; and a common source layer having a portion on an upper surface of the cover insulating layer.