3D Memory Array Architecture With BEOL-Integrated Sense Amplifiers
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Solution Overview
Problem
Current designs of three-dimensional (3D) memory devices with stacked memory arrays face challenges such as word line decoder overhead and the need for sense amplifiers for each bit line, leading to increased peripheral size and reduced density.
Innovation Solution
The 3D memory device integrates memory arrays, first sense amplifiers, and multiplexers within metallization layers, reducing the peripheral area and enhancing density by stacking these components in the back-end-of-line (BEOL) network.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If sense amplifiers are integrated into each metallization layer with memory arrays, then memory density is improved, but device complexity increases
Solution Approach 1:
The patent merges sense amplifiers with memory arrays by integrating them into the same metallization layers. Each metallization layer contains both memory cells and sense amplifiers, eliminating the need for separate sense amplifier chips or external components. This integration directly increases memory density while the shared metallization infrastructure manages the complexity through unified routing and control.
2Reliability
If multiple separate components are used for memory arrays and sense amplifiers, then functional performance is maintained, but peripheral size increases
Solution Approach 1:
The patent combines memory arrays and sense amplifiers into unified metallization layers, eliminating the need for separate peripheral components. The sense amplifiers are positioned within the same layers as memory cells, sharing routing paths and control structures, which significantly reduces the overall peripheral area while preserving full functional performance through integrated signal processing.
Solution Approach 2:
The patent transitions from a planar arrangement where sense amplifiers would be separate peripheral components to a three-dimensional stacked architecture where they coexist within the same metallization layers. This vertical integration in the BEOL (back-end-of-line) network reduces the footprint area by utilizing the third dimension (layer depth) for component placement.
3Quantity of substance
If traditional 3D stacked memory architecture is used, then memory capacity is increased, but routing complexity increases
Solution Approach 1:
The patent merges routing functions into the shared metallization layer infrastructure that also houses memory arrays and sense amplifiers. By combining all components in the same layers, the routing paths are simplified and standardized, reducing the complexity compared to traditional architectures where separate components require dedicated interconnects between layers.
Data Source
AI summary
A memory device includes a plurality of memory arrays, a plurality of first sense amplifiers, and a plurality of multiplexers. Each of the plurality of memory arrays includes a plurality of memory cells that are formed in a respective one of a plurality of metallization layers, which are disposed over a substrate. Each of the plurality of first sense amplifiers and a corresponding one of the memory arrays are formed in a respective one of the metallization layers. Each of the plurality of multiplexers, a corresponding one of the memory arrays, and a corresponding one of the first sense amplifiers are formed in the respective one of the metallization layers. Thus, the peripheral area of the memory device is reduced, thereby advantageously achieving higher density thereof.