3D Memory Tile Layout for Conductive Layer Bias Isolation
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in controlling bias applied to conductive layers due to capacitance generation between conductive layers and gate layers, leading to inefficiencies in data storage and retrieval.
Innovation Solution
The design isolates the conductive layer in one tile from the conductive layers in other tiles, allowing for precise control of bias application by omitting capacitances between them, and includes a stacked structure with ring-shaped channel pillars, source/drain pillars, and charge storage structures to enhance data storage efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conductive layers are placed adjacent to each other in multiple tiles, then area utilization and integration are improved, but capacitance generation between conductive layers and gate layers causes bias control issues
Solution Approach 1:
The memory device is divided into multiple independent tiles, where each tile contains its own conductive layer isolated from other tiles. This segmentation prevents capacitance coupling between adjacent tiles while maintaining high area utilization through vertical stacking of multiple tiles on the same substrate area.
Solution Approach 2:
An insulation layer is introduced as an intermediary between conductive layers of adjacent tiles to eliminate parasitic capacitance. This insulation layer acts as a mediator that physically separates the conductive layers, preventing electrical interference while allowing the structure to maintain compact integration.
2Reliability
If conductive layers in adjacent tiles are spaced apart to reduce capacitance, then bias control is improved, but device area increases
Solution Approach 1:
Instead of increasing horizontal spacing between conductive layers, the patent transitions to vertical stacking where multiple tiles are arranged in the vertical dimension. This allows conductive layers to be closely spaced horizontally while maintaining electrical isolation through the vertical insulation layers, thus preserving bias control without increasing device footprint.
3Productivity
If multiple tiles are integrated with conductive layers, then integration density is improved, but capacitance generation leads to operation inefficiency
Solution Approach 1:
The memory device is divided into multiple independent tiles, where each tile contains its own conductive layer isolated from other tiles. This segmentation prevents capacitance coupling between adjacent tiles while maintaining high area utilization through vertical stacking of multiple tiles on the same substrate area.
Solution Approach 2:
An insulation layer is introduced as an intermediary between conductive layers of adjacent tiles to eliminate parasitic capacitance. This insulation layer acts as a mediator that physically separates the conductive layers, preventing electrical interference while allowing the structure to maintain compact integration.
Data Source
AI summary
The present disclosure provides a three-dimensional memory device and a method for manufacturing the same. The three-dimensional memory device includes a plurality of tiles, and each tiles includes a plurality of blocks, and each blocks includes a gate stacked structure, a conductive layer, first ring-shaped channel pillars, source/drain pillars, and charge storage structures. The gate stacked structure is disposed on the substrate and includes gate layers electrically insulated from each other. The conductive layer is disposed between the substrate and the gate stacked structure. The first ring-shaped channel pillars are disposed on the substrate and located in the gate stacked structure. The source/drain pillars are disposed on the substrate, and each of the first ring-shaped channel pillars are configured with two source/drain pillars disposed therein. Each of the charge storage structures is disposed between the corresponding gate layer and the corresponding first ring-shaped channel pillar. The conductive layer in one of the tiles is isolated from the conductive layers in the other tiles.