3-D Memory BIST Circuit Synchronization via Master Die
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Solution Overview
Problem
The challenge in 3-D integration is the inefficient testing process due to the difficulty in accessing and synchronizing through-silicon via (TSV) connections, leading to increased test costs and degraded test quality in 3-D RAMs, as conventional BIST circuits face clock skew issues and asynchronous testing across dies.
Innovation Solution
A BIST circuit with an inter-die synchronization module and a test pattern generator that allows for synchronous testing across memory dies by designating a master die to send enable signals, ensuring all memory banks operate simultaneously, and utilizing a clock-domain-crossing-aware finite state machine to manage clock signals effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional BIST circuits are used in 3-D RAM, then each die can be tested independently, but clock skew and asynchronous testing occur across dies leading to degraded test quality
Solution Approach 1:
The patent merges the BIST control functions across multiple dies by designating one die as master and others as slaves. The master die's BIST circuit generates synchronized control signals that are distributed to all slave dies through TSV connections, enabling coordinated testing across the 3-D stack and eliminating clock skew issues between independent BIST circuits.
Solution Approach 2:
The patent introduces an intermediary synchronization mechanism where the master die acts as a mediator to coordinate testing across all dies. The master die generates enable signals and control patterns that are transmitted through TSVs to slave dies, ensuring all memory banks operate simultaneously and synchronously during testing.
2Ease of manufacture
If test pads are added to assist KGD test process, then TSV cannot be easily tested or contacted directly, but the number of test pads increases test cost and test time
Solution Approach 1:
The patent extracts the test function from external test pads and relocates it to built-in self-test circuits embedded within the memory dies themselves. Each die contains a BIST circuit that can generate test patterns and control testing internally, eliminating the need for additional external test pads and reducing test time while maintaining TSV testability.
3Productivity
If memory banks are tested asynchronously across dies, then testing can proceed independently, but simultaneous operation of memory banks cannot be ensured leading to corner-case conditions being missed
Solution Approach 1:
The patent implements periodic synchronized action across all memory banks by using a common clock signal distributed from the master die to all slave dies. This ensures that all memory banks operate in lockstep during testing, enabling simultaneous testing of corner-case conditions while maintaining efficient use of test resources through coordinated periodic operations.
Data Source
AI summary
A three-dimensional (3-D) memory includes: multiple memory dies, each having at least one memory bank and a built-in self-test (BIST) circuit; and a plurality of channels, for electrically connecting the memory dies. In a synchronous test, one of the memory dies is selected as a master die. The BIST circuit of the master die sends an enable signal via the channels to the memory dies under test. The BIST circuit in each of the memory dies is for testing memory banks on the same memory die or on different memory dies.