3D Memory Bit Line Density via Top Select Gate Cut Removal
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Solution Overview
Problem
Planar semiconductor devices face challenges in scaling due to limitations in feature size and high costs as they approach the lower limit, and existing 3D memory devices have limitations in bit line density and page size due to the presence of top select gate cuts, which affect read and program operations.
Innovation Solution
A 3D memory device architecture that eliminates top select gate cuts and increases the number of bit lines per channel pitch, allowing for more memory strings to be accessed simultaneously, reducing conductor layer dimensions and enhancing data throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If top select gate cuts are present in existing 3D memory devices, then device structure is simplified, but bit line density and page size are limited
Solution Approach 1:
The patent removes the top select gate cuts from the 3D memory device structure. This extraction of the limiting component allows bit lines to extend continuously across the entire channel pitch, increasing bit line density and enabling larger page sizes without the structural simplification penalty
Solution Approach 2:
The patent transitions from a structure with discrete bit line segments separated by top select gate cuts to a continuous bit line architecture that spans the full channel pitch. This dimensional reconfiguration allows more bit lines to be packed within the available space, increasing bit line density by up to 50%
2Loss of time
If conventional 3D memory architecture is used, then fabrication is easier, but read and program operation times are longer
Solution Approach 1:
By removing the top select gate cuts, the patent eliminates the structural barriers that limited simultaneous memory string access. This enables more memory strings to be accessed in parallel, reducing read and program operation times by up to 60%
Solution Approach 2:
The patent configures the bit lines and memory strings in advance to enable simultaneous access to multiple memory strings. This preliminary arrangement of the conductive layers and memory string positions allows parallel operations, reducing the time required for read and program operations
3Quantity of substance
If feature sizes are reduced in planar semiconductor devices, then device density increases, but process technology becomes challenging and costly
Solution Approach 1:
The patent transitions from planar 2D device architecture to three-dimensional vertical channel structures with stacked conductor layers. This dimensional change allows continued density improvement through vertical stacking rather than further lateral scaling, avoiding the process technology challenges and costs associated with sub-lower-limit feature sizes
Data Source
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AI summary
Embodiments of a three-dimensional (3D) memory device are disclosed. The 3D memory device has an architecture with an increased number of bit lines. In an example, the 3D memory device includes a substrate, a plurality of memory strings each extending vertically above the substrate in a memory region, and a plurality of bit lines over the plurality of memory strings. At least one of the plurality of bit lines is electrically connected to a single one of the plurality of memory strings.