3D Memory Bit Line Shielding for Read Throughput
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Solution Overview
Problem
In high-density 3D memory devices, capacitive coupling between adjacent global bit lines and bit line structures reduces read throughput, as only a quarter of bit lines can be accessed in one read operation due to shielding requirements.
Innovation Solution
The implementation of a memory device structure where odd and even bit line pairs are separated by an adjacent bit line pair, with bit line conductors having laterally offset portions to reduce capacitive coupling, allowing for simultaneous access to every other bit line structure and improving read throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple levels of memory cells are stacked to achieve high density, then storage capacity increases, but capacitive coupling between adjacent bit lines increases causing read throughput to decrease
Solution Approach 1:
The bit lines are segmented into odd and even bit lines that are alternately arranged and separated by shield bit lines. This segmentation reduces capacitive coupling between adjacent bit lines by inserting shielding structures between them, allowing more bit lines to be accessed in parallel during read operations.
Solution Approach 2:
Shield bit lines are introduced as intermediary structures between odd and even bit lines. These shield bit lines act as mediators that reduce capacitive coupling between adjacent bit lines by providing electrical shielding, thereby enabling higher read throughput without sacrificing storage capacity.
2Quantity of substance
If bit lines are arranged in close proximity to maximize density, then storage capacity increases, but capacitive coupling between adjacent bit lines increases requiring shielding that reduces the number of accessible bit lines
Solution Approach 1:
The bit line arrangement is segmented into alternating odd and even bit lines with shield bit lines positioned between them. This segmentation maintains close spacing for high density while creating accessible groups of bit lines that can be read simultaneously without excessive capacitive coupling.
Solution Approach 2:
Shield bit lines serve as intermediary elements that enable easier access to bit lines by reducing capacitive coupling. These intermediaries allow more bit lines to be accessed in parallel during read operations while maintaining the high-density arrangement.
3Productivity
If shielding structures are added to reduce capacitive coupling, then read throughput improves, but device complexity increases
Solution Approach 1:
The shielding function is merged with the existing bit line structure by using shield bit lines that are integrated into the same structural framework. This combining approach reduces device complexity compared to adding separate shielding layers, as the shield bit lines utilize the existing conductive and dielectric materials already present in the memory device.
Solution Approach 2:
The shield bit lines serve multiple functions: they provide capacitive shielding between odd and even bit lines, maintain the high-density arrangement, and integrate with the existing bit line structure. This multi-functionality reduces the need for additional separate shielding components, thereby limiting the increase in device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables half of the bit lines to be accessed in each read operation, significantly enhancing read throughput by minimizing capacitive coupling effects between global bit lines and bit line structures.
Implementation Method 1
capacitive coupling between adjacent global bit lines and adjacent bit line structures
Data Source
AI summary
A memory device includes a block of memory cells having a plurality of levels. Each level includes strips of memory cells extending in a first direction between first and second ends of the block. A first bit line structure, at each level at the first end, is coupled to a first string of memory cells extending from the first end. A second bit line structure, at each level at the second end, is coupled to a second string of memory cells extending from said second end. Bit line pairs extend in the first direction with each including odd and even bit lines. Odd and even bit line connectors connect the odd and even bit lines to the second and first bit line structures, respectively. Each bit line for a series of bit line pairs are separated by a bit line of an adjacent pair of bit lines.