3D Memory Bit Line Switches for High-Speed Sensing Accuracy
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Solution Overview
Problem
In high-speed data sensing operations of memory devices, the bit line voltage instability leads to extra offset current, affecting the accuracy of sensing results due to displacement currents during memory cell sensing.
Innovation Solution
A three-dimensional memory device design where the memory cell tile is divided into two sub-tiles, with specific bit line switches configuring selected and unselected memory cells to provide balanced loads to the sense amplifier, improving data reading accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-speed data sensing operation is performed, then sensing speed is improved, but bit line voltage stability deteriorates causing offset current
Solution Approach 1:
The memory cell tile is divided into two sub-tiles (first and second memory cell sub-tiles), each with dedicated bit line switches. This segmentation allows independent control of bit lines in each sub-tile, enabling better voltage stabilization during high-speed sensing operations by preventing mutual interference between adjacent bit lines.
Solution Approach 2:
Dedicated bit line switches are introduced as intermediary components between the global bit lines and the memory cells in each sub-tile. These switches act as mediators to isolate and stabilize the bit line voltage, preventing offset current generation during high-speed sensing while maintaining fast access to memory cells.
2Measurement precision
If load balancing on sense amplifier input terminals is improved, then sensing accuracy is improved, but device complexity increases
Solution Approach 1:
The memory cell tile is divided into two sub-tiles with dedicated bit line switches for each sub-tile. This segmentation creates symmetric load paths to the sense amplifier input terminals, ensuring balanced loading and improved sensing accuracy. The regular repeating structure of the segmented design helps manage complexity through modularity.
Solution Approach 2:
Different bit line switch configurations are applied to different sub-tiles based on their specific loading requirements. Each sub-tile has its own dedicated switches that are optimized for local load balancing, allowing the sense amplifier to receive balanced signals from both sub-tiles while maintaining overall system functionality.
Data Source
AI summary
A three dimension memory device, such as an AND-type memory, includes a memory cell tile, multiple source line switches, multiple first bit line switches to fourth bit line switches. The memory cell tile is divided into a first and a second memory cell sub-tiles. The first bit line switches are respectively coupled to multiple first bit lines of a first part of the first memory cell sub-tile. The second bit line switches are respectively coupled to multiple second bit lines of a second part of the first memory cell sub-tile. The third bit line switches are respectively coupled to multiple third bit lines of a first part of the second memory cell sub-tile. The fourth bit line switches are respectively coupled to multiple fourth bit lines of a second part of the second memory cell sub-tile.