3D Memory Bit Line Voltage Control for Read Speed
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Solution Overview
Problem
The longer settling time caused by parasitic capacitance in bit lines of 3D NAND memory devices slows down read operations, reducing the performance of memory devices.
Innovation Solution
A method for operating 3D memory devices involves performing read operations by applying a bit line voltage and maintaining it undischarged or partly discharged to a certain voltage level after detecting the data state of a memory cell, which is higher than half the bit line voltage, to reduce parasitic capacitance and improve settling time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the bit line is fully discharged after a read operation, then the memory cell data state can be accurately detected, but the parasitic capacitance causes longer settling time for the next read operation
Solution Approach 1:
The patent applies partial discharge action by maintaining the bit line voltage at a level between fully charged and fully discharged states. Instead of completely discharging the bit line after a read operation, the voltage is partially reduced to a level that preserves sufficient charge to minimize parasitic capacitance effects for the next read operation, while still allowing accurate data state detection. This partial action approach balances detection accuracy requirements with settling time reduction.
2Loss of time
If the bit line voltage is maintained at high level after read operation, then parasitic capacitance is reduced and settling time is shortened, but the voltage level must be carefully controlled to remain above half the bit line voltage
Solution Approach 1:
The patent changes the voltage parameter control strategy by defining a specific voltage range (above half the bit line voltage) for maintaining the bit line after read operations. This parameter change approach transforms the binary choice of fully charged/discharged states into a controlled intermediate voltage state, reducing parasitic capacitance effects while managing the complexity through established voltage thresholds.
3Device complexity
If conventional 2D NAND memory is used, then the structure is simpler, but it approaches physical limits and cannot achieve higher density and capacity
Solution Approach 1:
The patent transitions from two-dimensional NAND memory architecture to three-dimensional NAND memory architecture, adding a vertical dimension to the memory structure. This dimensional change enables stacking multiple memory layers vertically on a single die, achieving higher density and capacity without proportionally increasing the planar footprint, thus resolving the contradiction between structural simplicity and memory capacity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces parasitic capacitance and shortens the read time of 3D memory devices, enhancing their performance by maintaining the bit line voltage level after the first read operation, thereby improving the overall read time.
Implementation Method 1
The charging process can be affected by parasitic capacitance. For example, parasitic capacitance can cause the voltage level of a bit line to take a longer settling time.
Data Source
AI summary
A method for operating a three-dimensional (3D) memory device includes performing a first read operation for sensing a first memory cell of a first transistor string, and performing a subsequent second read operation for sensing a second memory cell of a second transistor string. Performing the first read operation includes applying a first bit line voltage to a first bit line, and maintaining the first bit line basically undischarged after data state of the first memory cell is detected.