3D Memory Bit Lines Between Elements and Peripheral Circuit
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Solution Overview
Problem
As three-dimensional memory devices scale down, the challenge arises in maintaining high performance due to the adverse impact of high temperature processing steps on peripheral logic circuitry, and the difficulty in process control for forming electrically conductive layers in high aspect ratio memory openings.
Innovation Solution
The solution involves forming bit lines between memory elements and peripheral circuits, using bit-line-connection via structures and pillar-shaped drain regions within an alternating stack of insulating and electrically conductive layers, which eliminates the need for complex processes at the bottom of high aspect ratio openings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If vertical semiconductor channels are connected to source line through pedestal channel structures at the bottom of each memory opening, then electrical connection is achieved, but process control difficulty increases due to high aspect ratio openings
Solution Approach 1:
The patent transitions from vertical connections at the bottom of high aspect ratio openings to lateral connections through bit lines positioned between memory elements. This dimensional shift eliminates the need for complex bottom-of-opening processes while maintaining electrical connectivity through a different spatial pathway.
Solution Approach 2:
The invention extracts the bit line formation process from the constrained environment of high aspect ratio memory openings and places it in the more accessible space between memory elements. This separates the bit line formation from the problematic pedestal channel formation, simplifying overall process control.
2Reliability
If high temperature processing steps are used to form electrically conductive layers, then memory device performance is improved, but peripheral logic circuitry is damaged
Solution Approach 1:
The patent segments the device into distinct regions: memory elements that undergo high temperature processing and peripheral logic circuits that remain protected. The bit lines and interconnect structures serve as thermal barriers, allowing differential thermal processing of different device sections.
Solution Approach 2:
The alternating stack of insulating and electrically conductive layers acts as an intermediary structure between the high temperature memory processing and the temperature-sensitive peripheral circuits. This layered structure enables thermal management while maintaining electrical functionality.
Data Source
AI summary
A three-dimensional semiconductor device includes bit lines formed in the lower-interconnect-level dielectric material layers located over a substrate, bit-line-connection via structures contacting a respective one of the bit lines, pillar-shaped drain regions contacting a respective one of the bit-line-connection via structures, an alternating stack of insulating layers and electrically conductive layers located over the pillar-shaped drain regions, and memory stack structures extending through the alternating stack. A source layer overlies the alternating stack, and is electrically connected to an upper end of each vertical semiconductor channel within a subset of the vertical semiconductor channels. Vertical bit line interconnections structures extending through the levels of the alternating stack may be eliminated by forming the bit lines underneath the alternating stack, and the footprint of the layout of the three-dimensional memory device may be reduced.