3D Semiconductor Memory Cell Layout for Low-Resistance Bit Line Contact
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Solution Overview
Problem
The integration of two-dimensional semiconductor devices is limited by the cost of fine pattern forming technology, making three-dimensional semiconductor memory devices with improved reliability and electrical characteristics necessary.
Innovation Solution
A semiconductor memory device with a stack structure featuring word lines and interlayer dielectric patterns alternately stacked on a semiconductor substrate, including semiconductor patterns between word lines, bit lines extending from the substrate, and memory elements between interlayer dielectric patterns, with specific source/drain regions and channel regions designed for enhanced electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional or planar semiconductor devices are used, then the structure is simple and manufacturing is easier, but integration is limited by the area occupied by unit memory cells and requires expensive fine pattern forming technology
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cells are stacked along the vertical direction (third direction) with word lines extending in the first direction and bit lines in the second direction, enabling higher integration density without requiring finer lateral patterning
2Productivity
If three-dimensional vertically stacked memory cells are used, then integration density is improved, but the electrical characteristics and reliability may be degraded without proper source/drain region design
Solution Approach 1:
The patent applies different width characteristics to different regions of the semiconductor pattern. The first source/drain region has a largest width greater than the channel region width to provide low resistance contact with bit lines, while the channel region maintains appropriate width for transistor operation. This local differentiation optimizes both electrical characteristics and reliability in the three-dimensional structure
3Reliability
If the first source/drain region has larger width, then contact resistance with bit line is reduced and electrical characteristics improve, but the device structure becomes more complex
Solution Approach 1:
The patent forms the semiconductor pattern with varying width characteristics before forming the word lines and interlayer dielectric patterns. The first source/drain region is preliminarily shaped with larger width to ensure low resistance contact with bit lines, and this width variation is maintained through subsequent processing steps, simplifying the overall device structure while improving electrical characteristics
Data Source
AI summary
A semiconductor memory device includes a stack structure including word lines and interlayer dielectric patterns that are alternately and repeatedly stacked on a semiconductor substrate. Semiconductor patterns are respectively disposed between vertically adjacent word lines. A bit line vertically extends from the semiconductor substrate and contacts the semiconductor patterns. A capping insulating pattern is disposed between the bit line and the word lines and covers side surfaces of the interlayer dielectric patterns. Memory elements are respectively disposed between vertically adjacent interlayer dielectric patterns. Each of the semiconductor patterns comprises a first source/drain region that contacts the bit line, a second source/drain region that directly contacts one memory element of the memory elements, and a channel region between the first and second source/drain regions. A largest width of the first source/drain region is greater than a width of the channel region.