3D Semiconductor Memory Stack With Protected Bit-Line Contacts
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Solution Overview
Problem
The integration of two-dimensional semiconductor devices is limited by the cost of advanced process equipment required for fine pattern formation, while three-dimensional semiconductor devices offer a solution but face challenges in reliability and electrical characteristics.
Innovation Solution
A semiconductor memory device with a stack structure featuring word lines and interlayer dielectric patterns, alternately stacked on a semiconductor substrate, includes semiconductor patterns between word lines, bit lines extending from the substrate, and memory elements between interlayer dielectric patterns, with specific source/drain regions and channel regions designed to enhance reliability and electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional or planar semiconductor devices are used, then manufacturing cost is reduced, but integration density is limited
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional vertically stacked memory cells. Multiple memory cell layers are stacked along the vertical direction, with word lines, bit lines, and interlayer dielectric patterns arranged in three dimensions. This dimensional change enables significantly higher integration density without requiring advanced fine pattern forming technology, thus avoiding the need for extremely expensive process equipment while achieving high-capacity memory storage.
2Quantity of substance
If three-dimensional semiconductor devices are used, then integration density is increased, but reliability and electrical characteristics deteriorate
Solution Approach 1:
The patent implements different material compositions and structural configurations in different regions of the three-dimensional memory device. The interlayer dielectric patterns have specific dielectric constants and material compositions optimized for their local function. The word lines and bit lines use different conductive materials with appropriate resistivity characteristics. The semiconductor patterns have controlled doping profiles varying by region. This local optimization ensures that each component maintains reliable electrical characteristics despite the three-dimensional architecture.
Solution Approach 2:
The patent incorporates preliminary structural designs during fabrication to ensure reliable electrical characteristics before final operation. The capping insulating patterns are formed in advance to protect and isolate conductive elements. The interlayer dielectric patterns are pre-configured with appropriate thickness and material properties to ensure electrical isolation and signal integrity. These preliminary actions during manufacturing establish the foundation for reliable device operation in the three-dimensional structure.
Data Source
AI summary
A semiconductor memory device includes a stack structure including word lines and interlayer dielectric patterns that are alternately and repeatedly stacked on a semiconductor substrate. Semiconductor patterns are respectively disposed between vertically adjacent word lines. A bit line vertically extends from the semiconductor substrate and contacts the semiconductor patterns. A capping insulating pattern is disposed between the bit line and the word lines and covers side surfaces of the interlayer dielectric patterns. Memory elements are respectively disposed between vertically adjacent interlayer dielectric patterns. Each of the semiconductor patterns comprises a first source/drain region that contacts the bit line, a second source/drain region that directly contacts one memory element of the memory elements, and a channel region between the first and second source/drain regions. A largest width of the first source/drain region is greater than a width of the channel region.