3D Memory Bit Line Layout for Lower-Capacitance Sensing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As memory cells are integrated at a high density, the loading capacitance on signal lines increases, making it difficult for bit line sense amplifiers to accurately sense voltage levels within the set sensing margin, and the complex semiconductor processes required to form precharge and select transistors on upper levels increase the area occupied by the core circuit region.
Innovation Solution
The memory device employs select transistors and precharge transistors formed using cell transistors from lower levels, reducing the loading capacitance on global bit lines and simplifying the semiconductor process by integrating these transistors vertically with existing cell transistors, thereby reducing the area occupied by the core circuit region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are integrated at high density, then storage capacity is improved, but loading capacitance on signal lines increases
Solution Approach 1:
The bit line is divided into multiple local bit lines, each connected to a separate sense amplifier. This segmentation reduces the loading capacitance on each individual bit line by limiting the number of memory cells connected to it, while still providing high storage capacity through the increased number of such segmented lines.
Solution Approach 2:
The patent introduces a third dimension by stacking memory cells vertically across multiple levels. This allows high storage capacity without proportionally increasing lateral loading capacitance, as each bit line can serve fewer cells laterally while accessing more cells vertically through the stacked structure.
2Adaptability or versatility
If precharge and select transistors are formed on upper levels, then device functionality is improved, but manufacturing process complexity increases
Solution Approach 1:
The cell transistors formed in lower levels are designed to serve dual purposes: as storage transistors for their primary memory function and as precharge/select transistors for bit line control. This multi-functionality eliminates the need for separate transistor structures on upper levels, reducing manufacturing complexity while maintaining full device functionality.
Solution Approach 2:
The patent merges the functions of storage transistors and control transistors into a single integrated structure. By combining these functions, the manufacturing process is simplified as only one type of transistor formation is required, while the device achieves both storage and control capabilities through proper circuit configuration.
3Measurement precision
If separate precharge and select transistors are added, then sensing capability is improved, but area occupied by core circuit region increases
Solution Approach 1:
The precharge and select transistors are positioned in the vertical dimension by utilizing lower levels for these functions while upper levels are dedicated to storage. This three-dimensional arrangement provides the necessary sensing capability without increasing the lateral area occupied by the core circuit region.
Solution Approach 2:
The cell transistors in lower levels perform both storage and control functions simultaneously. This multi-functionality eliminates the need for additional dedicated control transistor areas, maintaining compact core circuit region while preserving enhanced sensing capability through the shared transistor structures.
Data Source
AI summary
A memory device includes: local bit line structures arranged in first and second directions parallel to a surface of a substrate and intersecting each other, and extending across a plurality of vertical levels; first and second channel structures extending in the first direction on each of the plurality of levels and respectively contacting sidewalls of each of the local bit line structures and having first and second impurity regions; gate structures extending in the second direction on each of the plurality of levels, and respectively contacting the channel structures arranged in the second direction; cell capacitors in contact with the second impurity regions; first interconnection patterns respectively electrically connected to the second impurity regions on one or more first levels of the plurality of levels; and second interconnection patterns respectively electrically connected to the second impurity regions on the one or more first levels.