3D Semiconductor Memory Shielding Structure for Bit Line Capacitance
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Solution Overview
Problem
The accumulation of parasitic capacitance between stacked bit lines in three-dimensional dynamic random access memory (3D DRAM) structures affects electrical performance and can cause signal loss or errors, limiting memory density and stability.
Innovation Solution
A shielding structure is introduced between adjacent bit lines, comprising a body portion and shielding portions made of conductive material, which are electrically connected and grounded to reduce parasitic capacitance and improve electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple bit line structures are stacked in the vertical direction to increase memory density, then memory integration density is improved, but parasitic capacitance between stacked bit lines increases and electrical performance deteriorates
Solution Approach 1:
A shielding structure is introduced as an intermediary element between adjacent bit lines in the stacked configuration. This shielding structure, positioned in the space between bit lines, acts as a mediator that reduces the parasitic capacitance coupling between them, allowing the stacked architecture to maintain both high density and acceptable electrical performance
2Quantity of substance
If the quantity of stacked layers is increased to achieve higher integration density, then memory capacity is improved, but parasitic capacitance accumulation causes signal loss or malfunction
Solution Approach 1:
The shielding structure serves as a protective intermediary that prevents harmful capacitive coupling from accumulating as more layers are stacked. By positioning shields between bit lines across multiple stacked layers, the design maintains signal integrity and prevents malfunctions even as integration density increases
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The shielding structure effectively reduces parasitic capacitance, enhancing signal transmission and overall electrical performance while maintaining memory density and stability.
Implementation Method 1
there is parasitic capacitance between the stacked bit line structures
Implementation Method 2
a shielding structure including a body portion and multiple shielding portions, the multiple shielding portions extending in the second direction, where the body portion and the shielding portion each is formed of a conductive material
Data Source
AI summary
A three-dimensional semiconductor memory, includes a substrate, a plurality of active layers arranged in an array on the substrate, a plurality of bit lines, a plurality of storage nodes, and a shielding structure. Each of the bit lines is connected to one end of each of the active layers. The bit lines extend in a second direction, and are stacked on the substrate in a third direction. Each of the storage nodes is connected to the other end of each of the active layers. The shielding structure includes a body portion and a plurality of shielding portions. The shielding portions extend in the second direction. The body portion and the shielding portions each are formed of a conductive material, and the body portion is electrically connected to the shielding portions. At least one shielding portion is disposed between adjacent bit lines in the third direction.