3D Memory Array Stacking to Shorten Bit Lines and Save Chip Area
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in reducing the space factor of control circuits in three-dimensional memory arrays, leading to increased bit line length and capacity, which affects operation speed and chip area efficiency.
Innovation Solution
The semiconductor memory device integrates a three-dimensionally structured array chip without a substrate, where a circuit chip with a control circuit is stacked on top, connected via bonding metals and interconnection layers, allowing direct bit line and word line lead-outs to the control circuit, reducing interconnect length and chip area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the control circuit is provided right under the three-dimensional memory array to reduce space factor, then the chip area efficiency is improved, but the bit lines become substantially long causing increased bit line capacity and reduced operation speed
Solution Approach 1:
The patent transitions from a planar layout where control circuits are positioned under the array to a three-dimensional stacked architecture. The array chip and circuit chip are bonded together vertically, allowing bit lines to be led out directly to the control circuit in the stacked configuration, thereby reducing bit line length while maintaining compact chip area.
2Area of stationary object
If the control circuit is provided right under the three-dimensional memory array, then the space factor is reduced, but deep contact formation requires additional regions and increases manufacturing complexity
Solution Approach 1:
The patent divides the memory device into two separate chips: an array chip containing the three-dimensional memory array and a circuit chip containing the control circuit. This segmentation eliminates the need for deep contact formation through the array structure, simplifying the manufacturing process while achieving compact space utilization through vertical stacking.
3Area of stationary object
If bit lines are substantially long in the conventional configuration, then the chip area is efficiently utilized, but the bit line capacity increases and affects operation speed
Solution Approach 1:
By stacking the array chip and circuit chip vertically and bonding their surfaces, the patent creates a three-dimensional configuration where bit lines can be directly connected to the control circuit without extending across the entire chip area. This dimensional change reduces bit line length and capacity while maintaining efficient chip area utilization.
Data Source
AI summary
According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.