3D Memory Block Isolation Structure for Reliable Semiconductor Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing semiconductor devices face limitations in degree of integration and operational reliability due to the two-dimensional nature of memory cell formation on substrates, necessitating the development of three-dimensional semiconductor devices with improved structural stability and reliability.
Innovation Solution
The semiconductor device incorporates a first and second gate structure with stacked gate lines, an isolation insulating structure with stacked insulating plates and pillars, and a slit structure with irregular sidewalls, connected to the isolation insulating structure, to enhance electrical isolation and structural stability between memory blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If memory cells are formed in a single layer on a substrate, then the manufacturing process is simple, but the degree of integration reaches a limit
Solution Approach 1:
The patent transitions from two-dimensional single-layer memory cell formation to three-dimensional stacked memory cell structures. Multiple memory cells are vertically stacked on the substrate, increasing the degree of integration by utilizing the vertical dimension while maintaining manufacturing feasibility through standardized stacking processes
2Quantity of substance
If three-dimensional stacked memory cells are formed, then the degree of integration is improved, but structural stability and operational reliability become problematic
Solution Approach 1:
The stacked memory cell structure is divided into discrete memory cells separated by isolation insulating structures. These isolation structures segment the continuous stack into individual functional units, improving operational reliability by preventing interference between adjacent cells while maintaining the high integration benefits of the three-dimensional configuration
Solution Approach 2:
Isolation insulating structures serve as intermediary elements between adjacent stacked memory cells. These insulating structures electrically isolate neighboring cells, ensuring stable operation and preventing signal interference, thereby enhancing the overall reliability of the three-dimensional memory device
3Reliability
If isolation structures are added between memory blocks, then electrical isolation is improved, but device complexity increases
Solution Approach 1:
The isolation insulating structures are merged with the stacked memory cell formation process. The same vertical stacking methodology used for memory cells is applied to create the isolation structures, reducing overall device complexity by unifying manufacturing approaches while achieving effective electrical isolation between memory blocks
Data Source
AI summary
A semiconductor device may include: a first gate structure in a first memory block and including stacked first gate lines, the first gate lines extending from a plane center region to a plane edge region; a second gate structure in a second memory block adjacent to the first memory block and including stacked second gate lines, the second gate lines extending from the plane center region to the plane edge region; an isolation insulating structure located a) between the first gate structure and the second gate structure in the plane edge region, the isolation insulating structure including stacked insulating plates and insulating pillars extending through the insulating plates; and a slit structure located a) between the first gate structure and the second gate structure and b) in the plane center region, the slit structure connected to the isolation insulating structure, and including irregularities on a sidewall thereof.