3D Memory Block Vertical Stacking for Storage Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Two-dimensional memory arrays are approaching scaling limits, hindering further increases in storage density.
Innovation Solution
A three-dimensional memory block with multiple memory subarray layers stacked sequentially, featuring drain-region, channel, and source-region semiconductor layers, along with gate strips, enables row- and column-selection operations for read, write, and erase operations, enhancing storage density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional memory arrays are used, then device structure and control methods are simple, but storage density cannot be further increased due to scaling limits
Solution Approach 1:
The patent transitions from two-dimensional memory array layout to three-dimensional stacked memory subarray layers. Multiple memory subarrays are stacked vertically along the height direction, with each subarray containing semiconductor strips arranged in rows and columns. This vertical stacking enables significantly higher storage density by utilizing the third dimension (height) rather than only expanding in the planar directions.
2Quantity of substance
If three-dimensional stacked memory subarrays are implemented, then storage density increases, but device structure and control methods become more complex
Solution Approach 1:
The memory device is segmented into multiple independent memory subarrays stacked vertically. Each memory subarray contains semiconductor strips organized into rows and columns with associated word lines and bit lines. This segmentation allows each subarray to be addressed and controlled independently through row-selection and column-selection operations, managing the complexity of the three-dimensional structure by dividing it into manageable units.
Solution Approach 2:
The patent implements universal row-selection and column-selection operations that work across all memory subarrays. The control method uses standardized select signals (first select signal for row-selection, second select signal for column-selection) that can address any memory cell in any subarray uniformly. This multi-functional control approach simplifies the operation of the complex three-dimensional structure by providing a unified interface for all memory accesses.
Data Source
AI summary
The present disclosure provides a memory block and its control method. The method includes: performing row-selection operation on at least a portion of at least one row of multiple rows of word lines in the memory block to select at least a portion of at least one row of memory cells; performing column-selection operation on at least one column of memory cells of at least one of multiple memory subarrays to select at least one memory cells to perform a memory operation. The method enables read operation, write operation, and erase operation to perform on memory cells in a memory block with high storage density